Nonvolatile memory cell with vertical gate overlap and zero bird

Details Nonvolatile memory cell with vertical gate overlap and zero bird Nonvolatile memory cell with vertical gate overlap and zero bird

1995-06-06

1997-10-21

Nguyen, Viet Q.

Static information storage and retrieval

Floating gate

257315, 437 43, 437 49, H01L 21265, H01L 21225

Patent

active

056803451

ABSTRACT:
A memory device, such as a flash EEPROM, has zero birds' beaks and vertically overlapping gates to facilitate high cell density in the EEPROM's core. During fabrication, a layer of field oxide is formed over the core. The active regions are exposed by etching through the layer of field oxide to form vertically walled cavities around the active regions. The tunnel oxide, floating gate, interpoly dielectric, and the control gate are formed within each cavity so that the floating gate overlaps the control gate along the vertical walls. As a result, capacitive coupling between the gates is maintained, yet the horizontal dimensions of the cell decrease. Similarly, the absence of birds' beaks facilitates higher cell density in the core.

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"Electrical Properties for MOS LSI's Fabricated Using Stacked oxide SWAMI Technology," Sawada, et al., IEEE Transactions on Electron Devices, col. ED-32, No. 11, p. 2243, Nov., 1985.

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