Method of manufacturing an insulated gate field effect transisto

Details Method of manufacturing an insulated gate field effect transisto Method of manufacturing an insulated gate field effect transisto

1984-09-28

1986-09-09

Ozaki, George T.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 148187, 148188, 148189, H01L 2138

Patent

active

046100768

ABSTRACT:
In a method of manufacturing a semiconductor device, a thin silicon dioxide (SiO.sub.2) film for a gate insulation film and a polycrystalline silicon layer are successively deposited on a semiconductor substrate having one electrical conductivity type whereby this polycrystalline silicon layer has a gate electrode pattern. In this step a part of the polycrystalline silicon layer is left at a part where an electric contact with the substrate is to be formed. Parts of source and drain regions are formed by the self-align method with this polycrystalline silicon layer as a mask. A thick passivation film for an interlayer insulation film is formed to cover the whole surface. An aperture is formed selectively in the passivation film to expose the whole polycrystalline silicon layer at the part where the contact is formed. The polycrystalline silicon layer in the aperture part and the thin insulation film thereunder are removed to expose a part of the semiconductor substrate. An impurity is introduced into this exposed part to form a contact region overlapped with a part of the above-mentioned source and drain regions. Therefore, the aperture part for a contact with source and drain regions can be formed without a step of mask adjustment. Thus, a highly integrated function device can be easily realized.

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patent: 4366613 (1983-01-01), Ogura et al.
patent: 4397887 (1983-08-01), Aytac et al.
patent: 4404733 (1983-09-01), Sasaki
patent: 4433468 (1984-02-01), Kawamata
patent: 4443931 (1984-04-01), Baliga et al.
patent: 4498224 (1985-02-01), Maeguchi

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