Semiconductor device having planarized wiring

Details Semiconductor device having planarized wiring Semiconductor device having planarized wiring

1996-04-17

1997-10-21

Whitehead, Carl W.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257383, 257750, 257751, 437 47, 437 52, H01L 2348, H01L 2352

Patent

active

056799810

ABSTRACT:
A first contact hole and a second contact hole are formed in an insulating film on the surface of a substrate, and thereafter a blanket tungsten (W) layer is deposited on the substrate surface, with or without a barrier metal layer being interposed therebetween. The first contact hole has a small size a so that the W layer can fully bury the first contact hole, whereas the second contact hole has a large size b over a size c where a<c<b so that a desired wiring layer coverage ratio is attained. The deposited W layer is etched back while leaving the W layer in the first contact hole and a tapered W layer in the second contact hole. A wiring layer such as Al alloy is deposited on the substrate surface. The unnecessary wiring layer and barrier metal layer are patterned to form a wiring pattern. Wiring layers having a good burying state and a good coverage state can be obtained. A yield of manufacturing wiring layers can be improved.

REFERENCES:
patent: 4876223 (1989-10-01), Yoda et al.
patent: 5414302 (1995-05-01), Shin et al.
patent: 5519239 (1996-05-01), Chu

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