Method of making a CMOS dynamic random-access memory (DRAM)

Details Method of making a CMOS dynamic random-access memory (DRAM) Method of making a CMOS dynamic random-access memory (DRAM)

1994-12-30

1997-10-21

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 44, 437 56, H01L 218242

Patent

active

056795980

ABSTRACT:
A CMOS-technology, DRAM integrated circuit includes paired P-type and N-type wells in a substrate, which wells are fabricated using a self-aligning methodology. Similarly, FET's of the DRAM circuit are fabricated in the wells of the substrate using a self-aligning methodology to provide FET's of opposite polarity in a DRAM which may have paired memory cells and dummy cells for symmetry of circuitry. The DRAM includes a multitude of capacitor structures formed atop the FET's of the substrate, and plural layers of insulative dielectric with embedded bit and word traces providing for connection of the multitude of memory cells of the DRAM to external circuitry.

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