Method of fabricating a high resistance integrated circuit resis

Details Method of fabricating a high resistance integrated circuit resis Method of fabricating a high resistance integrated circuit resis

1996-02-01

1997-10-21

Nguyen, Tuan H.

Fishing, trapping, and vermin destroying

437 60, 437918, 437153, 437154, 148DIG136, H01L 21265

Patent

active

056795939

ABSTRACT:
The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created during NMOS source/drain implant may be counterdoped during PMOS source/drain implants and vice-versa. By appropriate choice of relative concentrations of a resistor dopant and counterdopant, and choice of diffusion depths, junction diodes can be formed which create a pinched resistor by constricting the current flow. The relative dopant concentrations can also be chosen to create regions of light effective doping within the diffusion resistor rather than creating junction diodes.

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T. C. Chen, et al., "Submicrometer Si and Si-Ge Epitaxial-Base Double-Poly Self-Aligned Bipolar Transisitors", IEEE Transactions On Electron Devices, vol. 38, No. 4, pp. 941-943; 124-127, (Apr. 1991).

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