Fishing – trapping – and vermin destroying
Patent
1995-12-18
1997-10-21
Niebling, John
Fishing, trapping, and vermin destroying
437 41, 437229, H01C 21265
Patent
active
056795920
ABSTRACT:
A process for forming a MOSFET, which includes the steps of: forming a gate insulating layer and a gate electrode on a semiconductor substrate, and forming lightly doped impurity regions on the left and right sides of the gate electrode and on the substrate; spreading photoresist, and forming a photoresist pattern for defining a side wall spacer formation portion on the gate electrode and on sides of the gate electrode; depositing an insulating layer on the surface of the substrate, and etching the insulating layer to remove an exposed surface portion and to form a side wall spacer on sides of the gate electrode; and removing the photoresist pattern, and forming a heavily doped source/drain region on the gate electrode and on sides of the side wall.
REFERENCES:
patent: 5032530 (1991-07-01), Lowrey et al.
patent: 5364807 (1994-11-01), Hwang
patent: 5395781 (1995-03-01), Wilhoit
Booth Richard A.
LG Semicon Co. Ltd.
Niebling John
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