Method for manufacturing semiconductor memory device having stac

Details Method for manufacturing semiconductor memory device having stac Method for manufacturing semiconductor memory device having stac

1991-11-18

1993-10-05

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 47, 437 60, 257303, 257309, 365149, 365185, H01L 2978, H01L 2992

Patent

active

052504581

ABSTRACT:
A dynamic RAM comprises an array of memory cells, each of the memory cells comprising a single access transistor and a charge storage region. The charge storage region comprises a first capacitor memory including a P.sup.+ region serving as an opposite electrode formed in the inner surface of a trench formed in a P type silicon substrate, a first capacitor dielectric film formed on the P.sup.+ region and a common electrode layer serving as a memory terminal formed on the first capacitor dielectric film, and a second memory capacitor including the common electrode layer, a second capacitor dielectric film formed on the common electrode layer and a cell plate electrode formed on the second capacitor dielectric film. The memory terminal and a drain region of the access transistor are connected in a self-aligning manner by an electrode having a sidewall shape which is in contact with an end of the memory terminal. Thus, a contact hole need not be formed in the first capacitor dielectric film, so that decrease of the electrical reliability of the first capacitor dielectric film can be prevented. The drain region of the access transistor may be formed by self-alignment with the contact portion of the common electrode layer.

REFERENCES:
patent: 4700457 (1987-10-01), Matsukawa
patent: 5006910 (1991-04-01), Taguchi
patent: 5012308 (1991-04-01), Hieda
patent: 5087588 (1992-02-01), Shimizu et al.
H. Sunami et al, "A Corrugated Capacitor Cell", IEEE Transactions on Electron Devices, vol. ED-31, No. 6, (Jun. 1984) 746, 753.

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