Zig-zagged plating bus lines

Details Zig-zagged plating bus lines Zig-zagged plating bus lines

1999-12-20

2001-11-20

Powell, William A. (Department: 1765)

Etching a substrate: processes

Forming or treating electrical conductor article

C216S020000, C216S033000

Reexamination Certificate

active

06319418

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of Printed Circuit Boards (PCB's) that are used with integrated circuit devices, and more particularly, to a method of creating and applying a non-linear plating bus geometry for the manufacturing of Printed Circuit Boards.
(2) Description of the Prior Art
Printed Circuit Boards (PCB's) are being used extensively in the creation of large semiconductor functional units. The PCB serves a number of different functions when used to mount semiconductor devices such as providing mechanical or structural support for the semiconductor devices, the ability to significantly increase the number of Input/Output (I/O) terminals and the ability to reduce thermal constraints that otherwise would be imposed on the semiconductor device. To enable the mounting of semiconductor devices on the surface of a PCB, different device packages have been developed. Among these different packages, the Quad Flat Package (QFP) and the Ball Grid Array (BGA) package are frequently used.
Quad Flat Packages (QFP) have in the past been used to create surface mounted high pin count integrated packages with various pin configurations. The electrical connections with these packages are typically established by closely spaced leads that are distributed along the four edges of the flat package. This limits the usefulness of the QFP since a high Input/Output (I/O) count cannot be accommodated in this manner. To address this problem, the Ball Grid Array (BGA) package has been created whereby the I/O points for the package are distributed not only around the periphery of the package but over the complete bottom of the package. The BGA package can therefore support more I/O points making this a more desirable package for high circuit density with high I/O count. The BGA contact points are solder balls that in addition facilitate the process of flow soldering of the package onto a printed circuit board. The solder balls can be mounted in an array configuration and can use 40, 50 and 60 mil spacings in a regular or staggered pattern.
In PCB manufacturing, multiple layers of printed circuits are created inside the printed circuit board. These layers are superimposed and are electrically isolated from each other. The printed circuits that make up the various layers of the PCB establish the electrical interconnections between the semiconductor devices and the surrounding circuitry. To facilitate the plating of printed circuits inside the PCB, plating bus lines are typically used. At the start of the PCB assembly process, the plating bus lines electrically short the whole PCB strip. During the process of separation or singulation of these matrix BGA's, these bus lines are mechanically removed by sawing through the bus lines. In this manner, the traces of the singulated units are electrically isolated. Current practice and present industry standards use bus lines that are straight lines. The indicated process of singulation using the straight bus lines results in the occurrence of copper particles or slivers during the sawing of these lines. These copper particles cause the singulated lines to be electrically shorted. Also, the straight bus lines that are currently used frequently cause electrical shorting of the semiconductor device due to uncut bus lines as a result of a slight shift in the (linear trajectory of the) cutting of the bus line. The invention provides a method that eliminates these problems and that therefore results in a significant improvement in the yield of manufacturing Printed Circuit Boards.
FIG. 1
shows a top view of a Prior Art process of cutting a bus line. The lines
12
and
14
form the printed circuit interconnect lines that form a layer within the PCB board. The bus line
10
is the (extraneous) line that is used to facilitate the plating of the printed circuit board. This line
10
is about 0.15 mm wide (
11
) and is to be removed by sawing; the width
13
of the cut of the sawing is about 0.25 mm. This process of removal results in the above indicated problems of electrical shorts between individual printed circuit lines
12
and/or
14
while it is clear that, if the singulation cut is not straight, parts of the bus line
10
will not be removed resulting in electrical shorts of devices that are to be mounted on the PCB.
SUMMARY OF THE INVENTION
A principle objective of the invention to provide bus line patterns that are used in the creation of Printed Circuit Boards that allow for the removal of the bus lines without creating extraneous particles of the removed bus lines and that therefore does not have a negative effect on PCB production yield.
In accordance with the objectives of the invention a new pattern is provided for the bus lines that are used to facilitate plating of layers of electrical lines that form a Printed Circuit Board. Where Prior Art bus lines have a straight-line geometry, the bus lines of the invention have any geometry that is not a straight-line. The geometry of the bus lines of the invention can be of any design as long as this design allows for interrupted cutting of the bus line, that is the cutting tool does not, during the process of cutting the bus line, make constant and continuous contact with the bus line.
U.S. Pat. No. 5,703,402(Chu et al. shows a BGA with buses or traces.
U.S. Pat. No. 5,777,381(Nishida) shows a packaging with bus lines.
U.S. Pat. No. 5,483,102(Neal et al.) shows a conventional package, such as a BGA, having bus lines.


REFERENCES:
patent: 5300168 (1994-04-01), Nakao et al.
patent: 5483102 (1996-01-01), Neal et al.
patent: 5703402 (1997-12-01), Chu et al.
patent: 5777381 (1998-07-01), Nishida

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