Zero voltage class AB minimal delay output stage and method

Details Zero voltage class AB minimal delay output stage and method Zero voltage class AB minimal delay output stage and method

2005-08-16

2005-08-16

Nguyen, Khanh V. (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including push-pull amplifier

C330S269000

Reexamination Certificate

active

06930551

ABSTRACT:
A class AB output circuit includes a P-channel pullup transistor (M13) having a source coupled to a supply voltage, a drain coupled to an output(10), a gate coupled to respond to an input signal on an input(9), an N-channel pulldown transistor (M1) having a drain coupled to the output, a source coupled to ground, and a gate coupled to respond to the input signal. A first N-channel transistor (M2) has a drain coupled to a gate of the output transistor and the supply voltage by means of a current source (8) and a source coupled to ground by means of a second current source (13). A first diode-connected N-channel transistor (M3), a second diode-connected N-channel transistor (M4), and a first level shifting circuit (17) are coupled in series between ground and a gate of the N-channel transistor, and a current source (7) is coupled between the first supply voltage and the gate of the first N-channel transistor. A second level shifting circuit (18) is coupled between the gate of the pulldown transistor and the source of the first N-channel transistor.

REFERENCES:
patent: 4570128 (1986-02-01), Monticelli
patent: 5894236 (1999-04-01), Mizoguchi et al.
patent: 6292057 (2001-09-01), Corsi et al.
patent: 6329878 (2001-12-01), Edwards et al.

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