Zero value-detecting circuit

Details Zero value-detecting circuit Zero value-detecting circuit

2005-08-23

2005-08-23

Phu, Phuong (Department: 2631)

Pulse or digital communications

Apparatus convertible to analog

C375S247000, C375S342000, C341S143000, C341S144000

Reexamination Certificate

active

06934324

ABSTRACT:
Provided is a circuit that has a simple circuit configuration and can detect zero values in a 1-bit digital signal irrespective of a recording medium such as SACD. DSD data forming the 1-bit digital signal are successively sent to a shift register (1) whose number of stages corresponds to the number of bits of an idle pattern such as “101010101” which appears when assuming a zero value. For example, the shift register (1) is an 8-bit shift register. An adder (2) sums up the values at each stages of the shift register (1). A zero decision circuit (4) produces an output indicating decision of zero if the sum value is half of the number of bits. A counter (5) keeps counting while the output indicating zero decision is being delivered. If the count value of the counter exceeds a given value, the counter produces an output indicating detection of a zero value. In consequence, zero values in a 1-bit digital signal can be detected with a simple circuit configuration, regardless of the idle pattern that varies among different recording media such as SACDs.

REFERENCES:
patent: 5682162 (1997-10-01), Hamasaki et al.
patent: 5889483 (1999-03-01), Tagami et al.

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