Zero-time-delay video processor circuit

Details Zero-time-delay video processor circuit Zero-time-delay video processor circuit

1991-11-01

1993-10-26

Mancuso, Joseph

Image analysis

Histogram processing

For setting a threshold

382 47, 358160, 358136, G06K 936, H04N 701

Patent

active

052573249

ABSTRACT:
A zero-time-delay video processor circuit includes reduction circuitry for eceiving a digital image input and providing a reduced and Nyquist acceptable digital image output signal. A controlled write/read memory connected to the reduction circuitry provides the digital image output. A digital estimator is connected to the reduction circuitry for providing an estimated gain signal. A gain corrector circuit is connected to the controlled write/read memory for compensating for errors in the estimated gain. A signal indicative of the true or required gain is provided to the digital estimator and to the gain corrector.

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patent: 4819190 (1989-04-01), Hinman et al.
patent: 4982285 (1991-01-01), Sugiyama

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