Zero static current high speed TTL compatible buffer

Details Zero static current high speed TTL compatible buffer Zero static current high speed TTL compatible buffer

1989-03-16

1991-09-03

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307475, 307263, 307279, 307530, H03K 1716, H03K 512, H03K 326

Patent

active

050457217

ABSTRACT:
A level discriminating buffer, including a input stage, a latching stage, and a switching accelerator, having an improved response time. The input stage discriminates between logic states of the input signal. The latch stage acts as a logic state latch and further provides transistors in the current paths of the input and latch stages that are non-conducting during each static state of the input signal. The switching accelerator is responsive to the input stage for generating a short period signal to accelerate the logic state switching of the latch stage and thereby improve the response of the output signal to a change in an input signal logic state change.

REFERENCES:
patent: 4354257 (1982-10-01), Varshney et al.
patent: 4486670 (1984-12-01), Chan et al.
patent: 4656374 (1987-02-01), Rapp

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