Zero standby current TTL to CMOS input buffer

Details Zero standby current TTL to CMOS input buffer Zero standby current TTL to CMOS input buffer

1985-05-28

1987-06-09

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307585, H03K 1710, H03K 19094

Patent

active

046722432

ABSTRACT:
A TTL to CMOS input buffer (20) which prevents static current flow when the TTL input signal is at a relatively low voltage logic "1" state. A transition detector (44) responsive to the input TTL logic signal and a voltage boosting circuit (50) connected between a positive power supply (VDD) and the input to a first CMOS inverter (30) are utilized to sense an input signal "0" to "1" transition and boost the TTL logic "1" signal to a voltage level which will prevent the p-channel transistor (32) included in the CMOS inverter from turning "on". The voltage boosting circuit will subsequently be disconnected from the input to the p-channel transistor to prevent the input from being fully charged to the positive power supply.

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patent: 4501978 (1985-02-01), Gentile et al.
patent: 4574273 (1986-03-01), Atsumi et al.
patent: 4584491 (1986-04-01), Ulmer

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