Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-10-05
2001-09-11
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S198000
Reexamination Certificate
active
06288584
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to complementary metal-oxide-semiconductor (CMOS) integrated circuits (IC's), and more particularly for power-on reset circuits.
BACKGROUND OF THE INVENTION
Integrated circuits have become increasingly complex. Sequential IC's use flip flops or registers to store state information. The registers can often be several layers deep within the circuit, requiring several clock cycles before data from the registers can be read by the external pins of the IC. Other circuits such as voltage regulators also have internal nodes that are not easily accessible to external pins.
When an IC is powered up, these internal nodes can power up to either high or low states, or even to an intermediate metastable state. Often parasitic capacitances and resistances of these internal nodes can determine the state after power up. Such indeterminate states after power up is quite undesirable, as circuit operation may not be determinate for several clock periods after power is applied. Testability is also difficult when IC's are not powered up to a known state.
Older IC's were reset after power was applied. An external reset input pin was used to assert a global reset signal that activated internal reset circuitry, such as NAND gates within internal flip-flops and registers. However, some IC's were limited in the number of available pins and could not be reset externally. Power-up-reset circuits were developed to automatically assert an internal reset signal as the power supply (Vcc or Vdd) was ramped up from ground.
A wide variety of power-on-reset circuits have been disclosed. See for example U.S. Pat. No. 5,180,926 by Skripek, and assigned to Sequoia Semiconductor Inc. of Scotts Valley, Calif. Many such circuits employed a resistive voltage divider.
FIG. 1
is a prior-art power-on reset circuit using a voltage divider. Such as circuit has been used in 1997-era CMOS chips. P-channel transistors
70
,
72
and n-channel transistor
74
form a voltage divider. The node A voltage of the gate of n-channel transistor
74
is set by the drain voltage of p-channel transistor
72
and n-channel transistor
74
. As Vcc rises up from zero volts to a Vcc of 3 or 5 volts, the voltage of node A rises. At first, when Vcc is less than 1 or 2 volts, the node A voltage of n-channel transistors
74
,
84
is less than 0.7 volt, the transistor threshold voltage. This keeps n-channel transistors
74
,
84
off. P-channel transistors
80
,
82
pull node B high, as does capacitor
10
, which is formed from a p-channel transistor with its drain and source connected to Vcc.
The high voltage of node B is inverted by transistors
30
,
32
to a low voltage on node C. Node C is also kept low by capacitor
16
, a n-channel transistor with its gate and drain connected to ground. Transistors
34
,
36
,
38
,
39
invert node C to generate a high on node D, which is also held near Vcc by capacitor
18
as Vcc rises. N-channel transistors
50
,
52
pull node E low, as p-channel transistors
40
,
42
remain off by the voltage of node D being near Vcc. N-channel transistors
54
,
56
are held off by the low node E, while p-channel transistors
44
,
46
turn on.
The low node E is inverted by transistors
62
,
64
and again by transistors
66
,
68
to generate a low reset signal
~
RST. The low
~
RST is routed to the many reset gates in the registers and flip-flops of the IC, causing these registers and flops to set or reset.
The low voltages on nodes C, E,
~
RST are near ground, while the high voltage on nodes B, D are near Vcc. Since Vcc is rising from ground to about 3 or 5 volts, the “high” voltage varies—it can be 1.0 volt when Vcc is 1.2 volts, or 1.5 volt when Vcc is 2 volts.
As Vcc rises above 1.5 to 2 volts, the voltage of node A rises to above 0.7 volt. Then n-channel transistors
74
,
84
turn on, since their gate-to-source voltages is above the transistor threshold voltage of 0.7 volt for a typical CMOS process. When n-channel transistor
84
turns on, it begins discharging node B and capacitor
10
. Once node B falls sufficiently, transistors
30
,
32
recognize node B as a low rather than a high, and drive node C high. Then transistors
34
,
36
,
38
,
39
drive node D low, while transistors
40
,
42
drive node E high. Some hysteresis is provided by transistors
44
,
46
. Eventually
~
RST is driven high, ending the reset pulse.
While such a power-on reset circuit is useful, it draws current even when not in use. The voltage divider of transistors
70
,
72
,
74
remain on even after full power is reached. Also, transistors
80
,
82
,
84
remain on, drawing still more current. Thus a small current is consumed during normal operation of the IC by the power-on-reset circuit. While the current is only 3 or 4 micro-amps, this can still drain batteries of very-low-power devices such as portable phones and computers.
Some zero-standby-power power-on-reset circuits have been developed. See for example, U.S. Pat. No. 5,936,444 by Pathak et al., and assigned to Atmel Corp. of San Jose, Calif. While useful, other zero-standby-power power-on-reset circuits are desired, especially for low-Vcc applications. Values of parasitic devices can vary significantly with process, temperature, and voltage variations, and power-up circuits are usually designed with large guard bands to ensure operation for worst-case conditions.
What is desired is a power-on-reset circuit for a CMOS IC that does not draw current after power is ramped up. A zero-power circuit is desired. A power-up circuit that has no direct paths from power to ground is desired to reduce standby current. A power-up circuit that is less sensitive to parasitic values is desirable.
SUMMARY OF THE INVENTION
A power-on-reset circuit has a capacitive-pullup divider that outputs a sensing voltage on a sensing node. The capacitive-pullup divider has a pullup capacitor between the sensing node and a power supply, and a transistor pulldown from the sensing node to a ground.
A charging transistor has a gate controlled by the sensing node. It drives a threshold node high when the sensing voltage drops. A charging capacitor is coupled between the threshold node and the ground. A discharge transistor is coupled between the threshold node and the ground. It discharges the charging capacitor before the charging transistor turns on.
A threshold stage receives the threshold node as an input. It inverts the threshold node to drive a trigger input. A series of inverters receives the trigger input. It generates a reset signal. A reset pulse is generated on the reset signal. The reset pulse ends in response to the sensing voltage falling when the transistor pulldown turns on when the sensing voltage reaches a predetermined voltage. Thus the reset pulse is generated by the capacitive-pullup divider.
In further aspects of the invention the pullup capacitor blocks direct current flow from the power supply to the ground through the transistor pulldown. The sensing node is connected to the ground only through the transistor pulldown. The sensing node is not connected to the power supply except through the pullup capacitor. The capacitive-pullup divider draws no direct current between the power supply and the ground, direct current being blocked by the pullup capacitor.
In still further aspects of the invention the series of inverters also generates a feedback signal. The feedback signal controls the discharge transistor. The discharge transistor is disabled by the feedback signal at an end of the reset pulse. The discharge transistor blocking current from the charging transistor to the ground. Thus current is blocked by the discharge transistor after the reset pulse ends.
In other aspects the transistor pulldown is a series of n-channel transistors. The series of n-channel transistors has gates connected to the sensing node. The series of n-channel transistors turns on, driving the sensing node to the ground, when the pullup capacitor pulls the sensing voltage above a sensing threshold as the power supply is ramped u
Kwong David
Wu Ke
Auvinen Stuart T.
Pericom Semiconductor Corp.
Tran Toan
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