Zero setup time flip flop

Details Zero setup time flip flop Zero setup time flip flop

1996-11-21

1999-02-02

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327201, 327218, H03K 3356

Patent

active

058670491

ABSTRACT:
Circuits and methods for a zero setup time storage element are disclosed. A storage element having a data input terminal, a clock input terminal and a data output terminal is able to capture a logic value of a data signal on the data input terminal with a substantially zero setup time at an active edge of a clock signal. Furthermore, some embodiments of the storage element are able to drive the captured logic value until the next active edge. One embodiment of the storage element includes a control circuit coupled to an output driver circuit. Depending on the state of the data input signal during an active edge, the control circuit can drives a first control signal to the output driver circuit or a second control signal to the output driver circuit. The output driver drives a data output signal on the data output terminal of the storage element based on the values of the control signals.

REFERENCES:
patent: 4629909 (1986-12-01), Cameron
patent: 5173618 (1992-12-01), Eisenstadt
patent: 5281865 (1994-01-01), Yamashita et al.
patent: 5497115 (1996-03-01), Millar et al.

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