Zero set-up high speed CMOS latched-receiver

Details Zero set-up high speed CMOS latched-receiver Zero set-up high speed CMOS latched-receiver

1998-10-28

2000-10-03

Cunningham, Terry D.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327218, H03K 3289

Patent

active

06127867&

ABSTRACT:
A latched receiver circuit capable of receiving data and clock simultaneously. New data is latched at every clock cycle without delay or buffering of the data or the clock. The latched receiver may also receive and latch small signals without the aid of a receiver preamp or added delay.

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patent: 5663669 (1997-09-01), Vanderschaaf
patent: 5668490 (1997-09-01), Mitra et al.
patent: 5982211 (1999-11-01), Ko

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