Zero result prediction

Details Zero result prediction Zero result prediction

1999-12-07

2003-09-30

Mai, Tan V. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S671000, C340S146200

Reexamination Certificate

active

06629118

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a zero result detector and a method of detecting a zero result.
2. Description of the Prior Art
The detection of a zero result during microprocessor operations is important as it may form a critical timing path, for example, in the control of conditional program execution. As an illustration, consider the situation where the result of a sum of two numbers is to be used as a denominator in a subsequent division operation, zero detection of the result can be used to avoid a division by zero in the subsequent operation and processing speed increased if this zero detection result is available sooner.
A zero detect function may generate a Boolean result that is TRUE, when the result of an arithmetic or logical operation has all bits set low, and FALSE when one or more bits are set high. This could be done by applying an N-bit wide NOR calculation to the output of an arithmetic logic unit (ALU) This is however slow, since the NOR function cannot begin until the result is available from the ALU. For a logical operation this may not be a problem, however, arithmetic operations tend to be a lot slower due, for example, to carry propagation and so the late availability of the zero detect becomes a limiting factor.
Measures that can increase the speed at which a zero detection result becomes available are strongly advantageous. Furthermore, it is important that early zero detection circuitry should not disadvantageously add to the size, cost and complexity of the system as a whole.
U.S. Pat. No. 5,604,689 and U. S. Pat. No. 5,020,016 both describe known early zero detect circuits.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention there is provided a zero result detector for detecting when the sum of a first number A, a second number B and a carry bit C is equal to zero, wherein A and B are binary numbers, the zero result detector comprising:
a first number generator operative to generate a number representing a negative value of A, −A;
a second number generator operative to generate a number representing a negative value of A minus 1, −A−1;
a selector operative to select the output of the, first number generator or the output of the second number generator in response to the value of the carry bit;
a comparator operative to generate a zero result signal indicative of the sum being zero in dependence upon a comparison of the selected value with the value of the second number B.
The device of the present invention provides a relatively simple mechanism for detecting a zero result without performing a complete arithmetic operation on the input numbers. The zero result is calculated in parallel to the arithmetic operation using the input operands to predict a zero, rather than performing a zero detection on the result of the addition. This can significantly increase the speed of processing of various operations.
In preferred embodiments operation of the first number generator, the second number generator and the selector is independent of the second number B such that the second number B may be input to said zero result detector later than the first number A.
The structure of the zero result detector of the invention makes it particularly effective in applications where one operand is available before a late arriving second operand. For example, in cases where the second operand B is barrel shifted prior to adding it to A.
Advantageously, the first and second number generators use 2's complement notation for representing negative values. 2's complement is a particularly effective notation for representing negative numbers as standard addition logic can correctly deal with such negative numbers.
In preferred embodiments, the second number generator for generating a number representing the negative value of A minus 1, comprises an inverter for inverting the first number A; and the first number generator for generating a number representing a negative value of A comprises an inverter for inverting the first number A and an incrementor for adding 1 to the output of the inverter.
This logical circuit provides an efficient manner of producing the required manipulated versions of the first number A.
Preferably, the inverter of the first number generator and the inverter of the second number generator are the same single inverter.
In accordance with a further aspect of the present invention there is provided a method of detecting a zero result of a sum of a first number A, a second number B and a carry bit C, wherein A and B are binary numbers, the method comprising the steps of: generating a first number representing a negative value of A, −A;
generating a second number representing a negative value of A minus 1, −A−1;
selecting either the first number or the second number in response to the value of the carry bit;
comparing the selected value with the value of the second number B; and
generating a zero result signal indicative of the sum being zero when the values are equal.


REFERENCES:
patent: 4648059 (1987-03-01), Gregorcyk
patent: 5144577 (1992-09-01), Linnenberg
patent: 5581496 (1996-12-01), Lai et al.
patent: 5604689 (1997-02-01), Dockser
patent: 6292818 (2001-09-01), Winters
patent: 61048038 (1986-03-01), None
patent: WO 96/10784 (1996-04-01), None

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