Zero-power CMOS non-volatile memory cell having an avalanche inj

Details Zero-power CMOS non-volatile memory cell having an avalanche inj Zero-power CMOS non-volatile memory cell having an avalanche inj

1999-06-15

2000-02-22

Tran, Andrew Q.

Static information storage and retrieval

Floating gate

Particular connection

3651851, 36518518, 36518527, 36518531, 365187, 365188, 257318, 257319, 257320, 257322, G11C 1604

Patent

active

060287896

ABSTRACT:
A zero-power non-volatile memory cell includes a control element, an avalanche injection element, and a CMOS inverter. A floating-gate electrode is capacitively coupled to the control element, the avalanche injection element, and to the CMOS inverter. The avalanche injection element is arranged, so as to transfer electrical charge onto the floating-gate electrode. The presence of stored data within the memory cell is indicated by reading a supply voltage V.sub.DD at an output terminal of the inverter. Accordingly, data can be read from the non-volatile memory cell without applying electrical power to the cell.

REFERENCES:
patent: 5101378 (1992-03-01), Radjy et al.
patent: 5754471 (1998-05-01), Peng et al.
patent: 5761116 (1998-06-01), Li et al.

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