Static information storage and retrieval – Powering
Reexamination Certificate
2005-08-02
2005-08-02
Nelms, David (Department: 2827)
Static information storage and retrieval
Powering
C365S063000
Reexamination Certificate
active
06925024
ABSTRACT:
A zero power standby mode in a memory device used in a system, such as a battery powered hand held device. By disconnecting the internal power supply bus on the memory device from the external power supply during standby mode, the junction leakage and gate induced drain leakage can be eliminated to achieve a true zero-power standby mode. A p-channel field effect transistor (FET) may be used to gate the external power supply such that the internal power supply bus on the memory device may be disconnected from the external power supply.
REFERENCES:
patent: 4496797 (1985-01-01), Price
patent: 4714977 (1987-12-01), Hoelzer et al.
patent: 4747600 (1988-05-01), Richardson
patent: 4906862 (1990-03-01), Itano et al.
patent: 4963769 (1990-10-01), Hiltpold et al.
patent: 5117129 (1992-05-01), Hoffman et al.
patent: 5192883 (1993-03-01), Kimura
patent: 5301160 (1994-04-01), McAdams
patent: 5359243 (1994-10-01), Norman
patent: 5465234 (1995-11-01), Hannai
patent: 5495182 (1996-02-01), Hardy
patent: 5517186 (1996-05-01), Veenstra
patent: 5532623 (1996-07-01), Advani et al.
patent: 5570050 (1996-10-01), Conary
patent: 5619412 (1997-04-01), Hapka
patent: 5664205 (1997-09-01), O'Brien et al.
patent: 5701268 (1997-12-01), Lee et al.
patent: 5721704 (1998-02-01), Morton
patent: 5723999 (1998-03-01), Merritt
patent: 5805909 (1998-09-01), Diewald
patent: 5828869 (1998-10-01), Johnson et al.
patent: 5956502 (1999-09-01), Manning
patent: 6052328 (2000-04-01), Ternullo et al.
patent: 6353599 (2002-03-01), Bi et al.
patent: 6388254 (2002-05-01), Trempala et al.
patent: 6404423 (2002-06-01), Kivela et al.
patent: 6438043 (2002-08-01), Gans et al.
patent: 6463055 (2002-10-01), Lupien et al.
patent: 6618825 (2003-09-01), Shaw
patent: 2001/0055984 (2001-12-01), Kawasaki et al.
patent: 2002/0008693 (2002-01-01), Banerjee et al.
patent: 2002/0008999 (2002-01-01), Hidaka
Higgins Brian P.
Lovett Simon J.
Pawlowski J. Thomas
Micro)n Technology, Inc.
Nelms David
Pham Ly Duy
Yoder Fletcher
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