Zero phase start optimization using mean squared error in a PRML

Details Zero phase start optimization using mean squared error in a PRML Zero phase start optimization using mean squared error in a PRML

1994-08-23

1996-09-03

Kim, W. Chris

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Data clocking

375369, 375376, G11B 509, H04L 2538, H03D 324

Patent

active

055529429

ABSTRACT:
A "zero phase start" optimization circuit for a Partial Response, Maximum Likelihood ("PRML") data channel dynamically determines a more optimal starting phase for the timing recovery process in a synchronous communication or storage system. The disclosed circuit includes a quantizer, a summing junction, either an absolute value or squaring function, and an integrator. A firmware based optimization routine causes a timing control loop to go through a series of timing acquisition modes, each time starting a clocking oscillator at different phase. The optimization circuit calculates the mean squared error between actual and expected sample values from a known frequency preamble pattern for each timing acquisition. The minimum MSE value corresponds to a more optimal starting phase for the timing control loop oscillator.

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