Zero overhead self-timed iterative logic

Details Zero overhead self-timed iterative logic Zero overhead self-timed iterative logic

1990-10-10

1992-06-09

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 3072722, 307279, 365203, 36518904, 365222, G11C 800

Patent

active

051210037

ABSTRACT:
CMOS domino logic is normally used only in two phases: precharge and logic evaluation. The invention uses a third phase to store data, which allows domino logic gates to be cascaded and pipelined without intervening latches. The inputs to this system must have strictly monotonic transitions during the logic evaluation phase and the precharge signal must be active during only the precharge phase. Furthermore, the pipelined system can feed its output back to the input to form an iterative structure. Such a feedback pipeline is viewed as a "loop" or "ring" of logic which circulates data until the entire computation is complete.

REFERENCES:
patent: 4631701 (1986-12-01), Kappeler et al.
patent: 4710650 (1987-12-01), Shoji
patent: 4747082 (1988-05-01), Minato et al.
patent: 4758990 (1988-07-01), Uchida
patent: 4856029 (1989-08-01), Geyer et al.
patent: 4999528 (1991-03-01), Keech

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