Zero latency-zero bus turnaround synchronous flash memory

Details Zero latency-zero bus turnaround synchronous flash memory Zero latency-zero bus turnaround synchronous flash memory

2000-06-30

2004-04-27

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S185110

Reexamination Certificate

active

06728161

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to non-volatile memory devices and in particular the present invention relates to a synchronous non-volatile flash memory.
BACKGROUND OF THE INVENTION
Memory devices are typically provided as internal storage areas in the computer The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programing and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modern personal computers (PCS) have their basic input/output system (BIOS) stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.
A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU's bus and is capable of running at 100 MHZ, about three times faster than conventional PPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAM's can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory device that can operate in a manner similar to SDRAM operation
SUMMARY OF THE INVENTION
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a method of writing to a synchronous non-volatile memory device is provided. The method comprises receiving write data on a first clock cycle and executing a data write operation, and executing a data read operation on a next clock cycle immediately following the first clock cycle.
Another method of operating a synchronous memory device comprises receiving write data on data connections, latching the write data in a write latch, releasing the data connections after the write data is latched, and performing a read operation on the synchronous memory device while the write data is transferred from the write latch to memory cells.
In yet another embodiment, a method of operating a synchronous memory device comprises receiving a read command and corresponding column address on a first clock cycle to request output data from a memory array of the synchronous memory. The output data is provided on an external data connection a predefined number of clock cycles following the first clock cycle. The method includes receiving a first command of a write command sequence on a second clock cycle immediately following the first clock cycle to initiate a write operation to the memory array such that the write command is provided in coincidence with or prior to providing the output data on the external data connection.
A synchronous memory device is provided in one embodiment and comprises a memory array arranged in rows and columns, data communication connections for bi-directional data communication with an external device, and a data buffer coupled to the data communication connections to manage the bi-directional data communication. A write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections.


REFERENCES:
patent: 4718041 (1988-01-01), Baglee et al.
patent: 5041886 (1991-08-01), Lee
patent: 5263003 (1993-11-01), Cowles et al.
patent: 5537354 (1996-07-01), Mochizuki et al.
patent: 5539696 (1996-07-01), Patel
patent: 5600605 (1997-02-01), Schaefer
patent: 5619456 (1997-04-01), McClure
patent: 5666321 (1997-09-01), Schaefer
patent: 5751039 (1998-05-01), Kauffman et al.
patent: 5787457 (1998-07-01), Miller et al.
patent: 5808946 (1998-09-01), Roohparvar
patent: 5835956 (1998-11-01), Park et al.
patent: 5892713 (1999-04-01), Jyouno et al.
patent: 5936903 (1999-08-01), Jeng et al.
patent: 5953280 (1999-09-01), Matsui
patent: 5995438 (1999-11-01), Jeng et al.
patent: 6026465 (2000-02-01), Mills et al.
patent: 6064627 (2000-05-01), Sakurai
patent: 6067255 (2000-05-01), Jung et al.
patent: 6081477 (2000-06-01), Li
patent: 6134143 (2000-10-01), Norman
patent: 6137133 (2000-10-01), Kauffman et al.
patent: 6141247 (2000-10-01), Roohparvar et al.
patent: 6154418 (2000-11-01), Li
patent: 6532522 (2003-03-01), Barth et al.
patent: 0 978 842 (2000-02-01), None
Keeth, et al., “DRAM circuit design: a tutorial,” IEEE Press, 2001, pp. 16-23, 142-153.
Micron Semiconductor Products, Inc., “2Mb, Smart 5 BIOS-Optimized Boot Block Flash Memory,”Flash Memorywww.micron.com, copyright 2000, Micron Technology, Inc., pp. 1-12.
Micron, “16 Mb: ×16 SDRAM”Synchronous DRAM, www.micron.com, copyright 1999 Micron Technology, Inc., pp. 1-51.
Patent Abstracts of Japan, Publication No. 2000048567, Publication Date Feb. 18, 2000.

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