Zero latency synchronized method and apparatus for system having

Details Zero latency synchronized method and apparatus for system having Zero latency synchronized method and apparatus for system having

1994-04-20

1996-08-20

Chin, Stephen

Pulse or digital communications

Synchronizers

375214, 375220, 375371, 375376, 327145, 327151, 327160, 327161, H04L 700

Patent

active

055486207

ABSTRACT:
A method and apparatus for implementing a zero latency synchronizer that permits the reliable transfer of data between clock domains by placing a metastability delay in the clock path. The zero latency synchronizer for synchronizing a signal from a first clock domain to a second clock domain is formed from a clock regenerator circuit and input and output master slave flip flops. The clock regenerator receives a first clock from the first clock domain and a second clock from the second clock domain and generates first and second regenerated clock signals. The first and second regenerated clock signals are formed in a manner that guarantees that the first and second regenerated clocks, in conjunction with the first and second clocks, can be used to control the input and output master slave flip flops and thereby pass data reliably from one clock domain to the other without delay. The master and the slave of the input flip flop are controlled respectively by the first clock domain clock and by the first regenerated clock. In turn, the master and slave of the output flip flop are respectively controlled by the second regenerated clock and by the second clock domain clock. A signal to be transferred from the first clock domain to the second clock domain is input to the master of the input flip flop. The output from the slave of the input flip flop is provided as input to the master of the output flip flop.

REFERENCES:
patent: 5142556 (1992-02-01), Ito
patent: 5256912 (1993-10-01), Rios
patent: 5369672 (1994-11-01), Matsumoto
patent: 5422914 (1995-06-01), Snyder

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