Zero-latency pipeline architecture for digital filters

Details Zero-latency pipeline architecture for digital filters Zero-latency pipeline architecture for digital filters

1996-09-17

1999-11-09

Moise, Emmanuel L.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708301, 708319, 708322, G06F 1710

Patent

active

059832541

ABSTRACT:
In a digital filter, data is received through an input path, and data in the filter is transported to an output through an output path. At least one delay element is disposed on the input path, and at least another delay element is disposed on the output path. The specific positions of the delay elements on the respective paths are selected to yield an optimal combination of filter parameters including the maximum computation delay, cost, and power consumption of the filter.

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C. Caraiscos, "Low-Latency Bit-Parallel Systolic VLSI Implementation of FIR Digital Filters," IEEE Transactions on Circuits and Systems--II: Analog and Digital Signal Processing, vol. 43, No. 7, Jul. 1996, pp. 529-534.

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