Boots – shoes – and leggings
Patent
1994-10-11
1996-12-03
Envall, Jr., Roy N.
Boots, shoes, and leggings
G06F 700
Patent
active
055814964
ABSTRACT:
Parallel processing architecture is used for an adder and its "look-ahead" zero-flag generator, which generates a flag signal for the most significant bit of the sum of the adder. The look-ahead zero-flag is generated with combinatorial logic circuits, which are fed from the addends and augents of the different bits for the adder and then decoded. The combinatorial logic circuits may comprise AND gates and XOR gates in a gate-array, and the decoder may be a programmable logic array (PLA). The computation time for the zero-flag thus generated is shorter than the computation time for the sum of the adder.
REFERENCES:
patent: 3983382 (1976-09-01), Weinberger
patent: 4878189 (1989-10-01), Kawada
patent: 4947359 (1990-08-01), Vassiliadis et al.
patent: 5020016 (1991-05-01), Nakano et al.
Chang Hwai-Tsu
Lai Shiang-Jhy
Envall Jr. Roy N.
Industrial Technology Research Institute
Lin H. C.
Ngo Chuong D.
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