Zero determination signal generating circuit

Details Zero determination signal generating circuit Zero determination signal generating circuit

2000-03-20

2003-02-18

Vo, Don N. (Department: 2734)

Pulse or digital communications

Testing

Reexamination Certificate

active

06522690

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a zero determination signal generating circuit which is mounted, together with a shifter, in an LSI and, generates a zero determination signal for determining whether or not the output data of the shifter is zero, i.e., whether or not all the bits in the output data are logic 0. (Logic 0 will be hereinafter referred to as “0”, and logic 1 as “1”.)
2. Description of the Related Art
A conventional zero determination signal generating circuit which performs an OR operation on all the bits in the output data of a shifter is often mounted, together with the shifter, in a LSI. However, the conventional zero determination signal generating circuit generates a zero determination signal after shifting operations of the shifter. This hinders a high-speed zero determining operation for the output of the shifter.
SUMMARY OF THE INVENTION
A general object of the present invention is to provide zero determination signal generating circuits, in which the above disadvantages are eliminated.
A more specific object of the present invention is to provide a zero determination signal generating circuit which can perform a zero determining operation for the output data of a shifter at high speed.
The above objects of the present invention are achieved by a zero determination signal generating circuit which generates a zero determination signal for determining whether output data of a shifter is zero, the shifter having first to xth left shifters cascaded where x is an integer of 3 or larger, an ith left shifter which is one of the first to xth left shifters having a 2
x
-bit structure and a shift amount of 2
x−i
bits or 0 bit, 2
x
-bit input data being applied to the first left shifter and 2
x
-bit output data being outputted from the xth left shifter, said zero determination signal generating circuit comprising:
j OR circuits where j=1, 2, . . . , x−1, a kth OR circuit which is one of the j OR circuits corresponding to the kth left shifter and performing an OR operation on bits of the 2
x
-bit data inputted to or outputted from the kth left shifter and located between a digit of the (2
x
−2
x−k
)th power of 2 and a digit of the (2
x
−2·2
x−k
+1)th power of 2; and
an OR/buffer circuit which performs, when the shift amount is 0 to 30, an OR operation on an output of a first one of the j OR circuits corresponding to one of the left shifters having a shift amount of zero, a bit of the 2
x
-bit data located at a digit of the (2
x
−1)th power of 2 and outputted from the xth left shifter when not performing a shifting operation, and a bit of the 2
x
-bit input data at a digit of 2
o
, and which performs, when the shift amount is 31, a buffering operation on the bit of the 2
x
-bit input data at a digit of 2
o
, the OR/buffer circuit outputting the zero determination signal.
With the above structure, an OR operation or a buffering operation is performed on predetermined bits in the 2
x
-bit input data to be inputted into left shifters having a shift amount of 0 or in the 2
x
-bit output data outputted from the left shifters having the shift amount of 0. The zero determination signal is then generated through an OR operation or a buffering operation by the OR/buffer circuit. In this manner, the zero determination signal can be generated at the same time that a shifting operation is carried out in the shifter.
The above objects of the preset invention are also achieved by a zero determination signal generating circuit which generates a zero determination signal for determining whether output data of a shifter is zero, the shifter having first to xth right shifters cascaded where x is an integer of 3 or larger, an ith right shifter which is one of the first to xth right shifters having a 2
x
-bit structure and a shift amount of 2
x−i
bits or 0 bit, 2
x
-bit input data being applied to the first right shifter and 2
x
-bit output data being outputted from the xth right shifter, said zero determination signal generating circuit comprising:
j OR circuits where j=1, 2, . . . , x−1, a kth OR circuit which is one of the j OR circuits corresponding to the kth right shifter and performing an OR operation on bits of the 2
x
-bit data inputted to or outputted from the kth right shifter and located between a digit of the (2
x−(i−1)
−2)th power of 2 and a digit of the (2
x−i
−1)th power of 2; and
an OR/buffer circuit which performs, when the shift amount is 0 to 30, an OR operation on an output of a first one of the j OR circuits corresponding to one of the right shifters having a shift amount of zero, a bit of the 2
x
-bit data located at a digit of the 2
o
and outputted from the xth right shifter when not performing a shifting operation, and a bit of the 2
x
-bit input data at a digit of the (2
x
−1)th power of 2, and which performs, when the shift amount is 31, a buffering operation on the bit of the 2
x
-bit input data at a digit of the (2
x
−1)th power of 2, the OR/buffer circuit outputting the zero determination signal.
With the above structure, an OR operation or a buffering operation is performed on predetermined bits in the 2
x
-bit input data to be inputted into right shifters having a shift amount of 0 or in the 2
x
-bit output data outputted from the right shifters having the shift amount of 0. The zero determination signal is then generated through an OR operation or a buffering operation by the OR/buffer circuit. In this manner, the zero determination signal can be generated at the same time that a shifting operation is carried out in the shifter.
The above objects of the present invention are also achieved by a zero determination signal generating circuit which generates a zero determination signal for determining whether output data of a shifter is zero, the shifter having a left shifter unit, a right shifter unit, and an output data selector,
the left shifter unit having first to xth left shifters cascaded where x is an integer of 3 or larger, an ith left shifter which is one of the first to xth left shifters having a 2
x
-bit structure and a shift amount of 2
x−i
bits or 0 bit, 2
x
-bit input data being applied to the first left shifter and 2
x
-bit output data being outputted from the xth left shifter,
the right shifter unit having first to xth right shifters cascaded where x is an integer of 3 or larger, an ith right shifter which is one of the first to xth right shifters having a 2
x
-bit structure and a shift amount of 2
x−i
bits or 0 bit, 2
x
-bit input data being applied to the first right shifter and 2
x
-bit output data being outputted from the xth right shifter,
the output data selector which selects and outputs the output data of the left shifter unit when the shifter functions as a left shifter, and which selects and outputs the output data of the right shifter unit when the shifter functions as a right shifter,
said zero determination signal generating circuit comprising:
j left-shifter OR circuits where j=1, 2, . . . , x−1, a kth left-shifter OR circuit which is one of the j left-shifter OR circuits corresponding to the kth left shifter and performing an OR operation on bits of the 2
x
-bit data inputted to or outputted from the kth left shifter and located between a digit of the (2
x
−2
x−k
)th power of 2 and a digit of the (2
x
−2·2
x−k
+1)th power of 2;
a left-shifter OR/buffer circuit which performs, when the shift amount is 0 to 30, an OR operation on an output of a first one of the j left-shifter OR circuits corresponding to one of the left shifters having a shift amount of zero, a bit of the 2
x
-bit data located at a digit of the (2
x
−1)th power of 2 and outputted from the xth left shifter when not performing a shifting operation, and a bit of the 2
x
-bit input data at a digit of 2
o
, and which performs, when the shift amount is 31, a buffering operation on the bit of the 2
x
-bit input data at a digit of 2

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