Data processing: financial – business practice – management – or co – Miscellaneous
Reexamination Certificate
1999-06-09
2002-07-23
Mai, Tan V. (Department: 2121)
Data processing: financial, business practice, management, or co
Miscellaneous
Reexamination Certificate
active
06424955
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to digital processors in general and to zero detection, for example in the output of an Arithmetic Logic Unit (ALU) in particular. Instructions in digital processors are often conditionally executed based on processor status and zero detection is an important part of status generation in such processors.
Virtually all digital processors contain zero detection logic to indicate whether the result of an arithmetic operation is zero. Programmers often use the stored zero detection result, commonly called the zero flag, and other status flags to decide how a program should behave in run-time.
The conventional manner of generating the zero flag value is to place a zero detection circuit after an adder and/or subtractor, as shown in FIG.
1
. As shown in
FIG. 1
, the adder/subtractor (+/−) has a number of inputs (Add-Sub, A, B, c) and an output (R) which is input to the zero detection circuit
10
. The zero detection circuit outputs a zero flag value (usually 1 or 0) to the zero flag position in a status register
12
.
A disadvantage of the conventional arrangement is that the zero detection circuit is added to the output path of the adder/subtractor which path is often a critical path in the processor logic. As such the zero detection circuit adds a delay in the critical processing path and this degrades the processor performance. Attempts have been made to mitigate this problem by introducing an additional and so-called processor pipeline stage. This, however, has the drawback of adding significantly to the complexity of the processor and of incurring additional cost.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention there is provided a digital processor having an arithmetic unit and a zero detection circuit wherein the zero detection circuit sets a zero flag when the output value from the arithmetic unit is zero, characterised in that the zero detection circuit is connected to the input of the arithmetic unit so as to enable testing of the input to the arithmetic unit independently of the arithmetic unit itself thereby to detect when the output value from the arithmetic unit is zero.
According to a second aspect of the present invention there is provided a method of performing zero detection in a digital processor so as to set a zero flag when the output value from an arithmetic unit of the processor is zero, comprising the step of connecting a zero detection circuit to the input of the arithmetic unit and testing the input to the arithmetic unit independently of the arithmetic unit itself so as to detect when the output value from the arithmetic unit is zero.
REFERENCES:
patent: 3983382 (1976-09-01), Weinberger
patent: 4618956 (1986-10-01), Horst
patent: 5020016 (1991-05-01), Nakano et al.
patent: 5367477 (1994-11-01), Hinds et al.
patent: 5561619 (1996-10-01), Watanabe et al.
patent: 5581496 (1996-12-01), Lai et al.
patent: 5586069 (1996-12-01), Dockser
patent: 5862065 (1999-01-01), Muthusamy
patent: WO 96/10784 (1996-04-01), None
LSI Logic Corporation
Mai Tan V.
Westman Champlin & Kelly
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