Zero detection circuitry and methods

Details Zero detection circuitry and methods Zero detection circuitry and methods

1997-11-14

1999-11-02

Malzahn, David H.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 700, G06F 750

Patent

active

059788259

ABSTRACT:
A method of generating zero detect flag at the output of an adder adding a first vector and a second vector to generate a third vector. A fourth vector is generated from the third vector a carry propagation vector and a carry generation vector. A fifth vector generated using an incremented third vector and an incremented carry propagation vector. A sixth vector generated from the fourth vector and the fifth vector. The bits of the sixth vector bitwise added to obtain the zero detection flag.

REFERENCES:
patent: 5270955 (1993-12-01), Bosshart et al.
patent: 5561619 (1996-10-01), Watanabe et al.
patent: 5581496 (1996-12-01), Lai et al.
patent: 5586069 (1996-12-01), Dockers

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