Zero detect for binary difference

Details Zero detect for binary difference Zero detect for binary difference

1996-08-08

2000-01-25

Malzahn, David H.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708211, G06F 700, G06F 750

Patent

active

060187573

ABSTRACT:
Zero detect of a difference of binary operands is disclosed. If the difference is zero, the bit-complement of the difference is a string of one's, and therefore incrementing the string of one's generates a carry-out bit of one. Likewise, if the difference is non-zero, the bit-complement of the difference will contain one or more zero's, and therefore incrementing the bit-complemented difference will generate a carry-out bit of zero. The operands include a minuend and M subtrahends. One embodiment includes providing a result representing a bit-complement of the difference, and then inspecting a carry-out bit generated by incrementing the result. Another embodiment includes bit-complementing the minuend, generating a first carry-out bit from a sum of the bit-complemented minuend and the M subtrahends, generating a second carry-out bit from a sum of the bit-complemented minuend and the M subtrahends and a constant of one, and setting a zero detect flag to TRUE when the first and second carry-out bits have different logical values. Advantageously, the first and second carry-out bits can be generated concurrently using propagate-generate sections coupled to carry chains to provide rapid zero detect. The invention is well-suited for providing zero detect of the difference A-B where A and B are n-bit binary operands, as well as zero detect of the difference A-B-C where A and B are n-bit binary operands and C is a carry-in bit.

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