Zero cancellation in multiloop regulator control scheme

Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...

Reexamination Certificate

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C323S281000, C323S315000, C323S316000, C323S276000, C323S277000, C323S274000, C361S093900, C361S126000, C330S297000, C330S257000, C330S292000, C330S107000

Reexamination Certificate

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07323854

ABSTRACT:
Control loops in a voltage regulator can be stabilized using minimal silicon area. A current limit signal, generated by a current limit control loop in the voltage regulator, can be divided to minimize a zero provided in a compensation set associated with a voltage control loop, thereby stabilizing both loops. The compensation set can include a resistor (the zero) and a capacitor (a pole) connected in series between output and input terminals of an amplifier. Dividing the current limit signal can include injecting a first portion of the current limit signal on a first side of the resistor and injecting a second portion of the current limit signal on a second side of the resistor. The ratio of the first and second portions can be based on a gain of the amplifier, thereby minimizing an effect of the resistor.

REFERENCES:
patent: 3983502 (1976-09-01), Wheatley, Jr.
patent: 4949054 (1990-08-01), Briefer
patent: 5945818 (1999-08-01), Edwards
patent: 6556083 (2003-04-01), Kadanka
patent: 6861827 (2005-03-01), Yang et al.
patent: 2007/0096825 (2007-05-01), Okuyama
patent: 0564983 (1993-10-01), None
patent: 10256838 (1998-09-01), None

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