Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-10-01
2002-11-26
Mai, Tan V. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06487576
ABSTRACT:
This application claims priority to S.N. 98402457.0, filed in Europe on Oct. 6, 1998 and S.N. 98402455.4, filed in Europe on Oct. 6, 1998.
FIELD OF THE INVENTION
The present invention relates to zero anticipation in the field of computing systems. In particular, the invention relates to a zero anticipation mechanism, to a processing engine and a computing system including such a mechanism and to a method of zero anticipation in such apparatus.
BACKGROUND OF THE INVENTION
Where reference is made to a computing system, it should be understood that this term is intended to relate generally to systems and apparatus which perform computations, including computers and electronic apparatus including processing engines for performing computations, and to the processing engines themselves. Many different types of processing engines are known, including the central processing units of mainframe systems, microprocessors, micro-controllers, digital signal processors and so on.
The performance of a computing system is vitally affected by the speed and accuracy with which arithmetic operations are performed in the processing engine. This is because many of the instructions executed by a processing engine of such a computing system require arithmetic operations. Arithmetic circuitry is often the most complex circuitry in the instruction execution unit of a processing engine in terms of the number of gates and logic levels. In relative terms, therefore, arithmetic operations tend to be slow and prone to error. One important aspect of the result of arithmetic operations is the determination of condition codes.
A condition code will be set by the processing engine to reflect the outcome of an arithmetic operation. This code assists the processing engine in making operational decisions which depend upon arithmetic results. A typical processing engine, such as a microprocessor or a digital signal processor for example, has an arithmetic logic unit (ALU) which performs mathematical operations on two or more “N” bit operands, where “N” represents the total number of bits per operand. It will be convenient in the following to refer to the “i”th bit, where “i” is an index variable whose value is between 0 and N−1 inclusive.
One type of computation result on which a decision, such as for example branch decision, might be made is where the operation result is a zero condition. For example, a branch might be made if the result of a computation is zero, whereas program execution might otherwise continue at the next command. Alternatively, the converse may be true.
Typically, the decision as to whether to take a branch or not will rely on the resolution of the computation result (e.g., whether the result is zero or not). As, however, this may take some time and, also, the branch operation itself will take some time, this can have a not insignificant effect on overall system performance.
Condition codes are also important in some non-arithmetic operations, for example a conditional data operation where the destination of a result will depend upon the resolution of the condition. An example of this could, for example, be a data load instruction involving the generation of data complements. Once again, the time taken to resolve the condition and then to effect the operation dependent thereon can have a not insignificant effect on performance.
The condition code may, for example, be employed to indicate that the result of an operation is greater than zero (GT), less than zero (LT), or equal to zero (EQ). LT is the easiest outcome to detect, because it simply involves examining the sign bit of the result. In general, GT and EQ are more difficult outcomes to detect, because the sign bit of the result is set positive when the result is either zero or a positive quantity. Therefore, examining the sign bit of the result, when the result is equal to zero, does not indicate whether the result is zero or a positive number. However, for the result of a specific instruction on specific data, EQ and GT are mutually exclusive. Thus, determining one is sufficient for the determination of the other, once LT has been excluded.
In adder operation, the traditional method of determining when the result is zero is to NOR all of the output bits of an adder circuit to reduce as fast as possible the output bits to a single output (zero) using a binary tree. However, as many architectures require 32-bit, or wider, data path for fixed point units, they also require adders of 32 bits in width. The NORing all of the output bits may require two or more additional stages of logic, depending on the technology used for implementation. For example, to reduce 32 bits would take five stages with two input NOR gates (2
5
=32) and three stages with four input NOR gates (4
3
=64). As higher clock rates are demanded, the addition of logic stages to an adder circuit can result in the condition code becoming critical, thereby forcing completion of its computation into the next machine cycle.
Several solutions have been proposed for determining when a result is zero. For example, U.S. Pat. No. 4,924,422 issued May 8, 1990 to IBM Corporation describes a method and apparatus for determining when a result is zero. This patent determines when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another embodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit reduces the gate delay and gate count allowing the processor central processing unit to determine the condition prior to the actual sum of two operands. This allows the processing engine to react to the condition more quickly, thus increasing overall operating speed.
U.S. Pat. No. 4,815,019, issued Mar. 21, 1989 to Texas Instruments, Inc., describes a method and apparatus for determining when an ALU result is zero. This patent describes a fast ALU=0 circuit that is used with a carry-select look ahead ALU. Preliminary ALU=0 signals are derived for each section of the ALU prior to a carry in signal being received by that section. When the carry in signal is received, a final comparison is made with the least significant bit of the section and the final ALU=0 signal is generated. The ALU=0, computation is completed one gate delay after the ALU computation is completed. The circuit for computing whether the result of an ALU computation is zero determines whether certain bits are zero before the ALU computation is complete. When the final ALU computation is available, only a very small number of bits need be considered to determine whether the result is zero. This determination is made with the insertion of only 1 additional gate delay after the ALU computation is complete.
U.S. Pat. No. 5,508,950, issued Apr. 16, 1996 to Texas Instruments, Inc., describes a circuit and method for detecting when an ALU result is zero. This patent describes a circuit and method for detecting if a sum of a first multi-bit number A of N bits and a second multi-bit number B of N bits equals a third multi-bit number C of N bits prior to availability of the sum of A and B. A propagate signal, a generate signal and a kill signal are generated for each bit in the proposed sum. A zero signal is formed from these signals. The particular manner of forming the zero signal for each bit depends upon the state of the third multi-bit number C for the corresponding bit and the prior bit. The zero signal is an exclusive OR of the corresponding propagate signal P
n
and a kill signal K
n−1
of a prior bit if the current bit and the prior bit of C are “00”. The zero signal is an exclusive NOR of t
Catan Herve
Giacalone Jean-Pierre
Lombardot Anne
Brady III W. James
Laws Gerald E.
Mai Tan V.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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