Active solid-state devices (e.g. – transistors – solid-state diode – Tunneling pn junction device – Reverse bias tunneling structure
Reexamination Certificate
1999-04-30
2001-07-17
Mintel, William (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Tunneling pn junction device
Reverse bias tunneling structure
C257S532000, C257S533000, C257S536000, C257S537000, C257S603000
Reexamination Certificate
active
06262442
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to semiconductor devices and integrated circuits and fabrication methods therefor, more specifically, this invention relates to an improved zener diode and RC network combination semiconductor device in an integrated circuit and a method for manufacturing such an improved zener diode and RC network combination semiconductor device which provides voltage reference for active and/or passive devices or circuits or any type of integrated circuit.
2. Description of the Related Art
In the prior art, various types of zener diodes and methods for manufacturing zener diodes have resulted in a compromise between accuracy of the voltage reference and complexity of the fabrication process. Buried zener diodes, i.e. the PN junction is below the surface of the substrate, as found for example in U.S. Pat. No. 5,241,213 “Buried Zener Diode Having Auxiliary Zener Junction Access Path”. (Hull) proffers to have increased voltage reference accuracy, but certainly at the expense of added complexity.
Another example of a more rudimentary buried zener diode appears in U.S. Pat. No. 4,910,158 “Zener Diode Emulation And Method Of Forming The Same” (Anderson). The Anderson reference discloses a zener diode pair.
The prior art which also includes U.S. Pat. No. 4,853,759 (Haque), U.S. Pat. No. 5,355,014 (Rao et al.), U.S. Pat. No. 5,770,886 (Rao et al.), U.S. Pat. No. 5,218,222 (Roberts), U.S. Pat. No. 5,227,012 (Brandli et al.) and Japanese Document 58-868 (04/1987) H01L27/04, disclose prior configurations. However, none of these prior references disclose the combination of features of the combined semiconductor integrated circuit device of this invention and the fabrication method therefor.
Furthermore, none of the prior art seeks to leverage the advantages of providing a zener diode with an RC network in one integrated circuit using all front side electrical contacts. Therefore a need existed to optimize a semiconductor structure and fabrication technique for providing a zener diode in combination with an RC network in one integrated circuit combination without using the backside of the semiconductor substrate by using the top or front side of the semiconductor substrate to make electrical contact to all of the devices including the active zener diode device, the passive resistor device and the passive capacitor device. This would facilitate use of such a semiconductor structure in a “Flip-Chip” type package or a backside mounted (die bonding) configuration because all of the electrical contacts are made to just one (top or front) side of the semiconductor substrate.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved semiconductor device comprising at least one zener diode and an RC network and a fabrication method therefor.
It is another object of the present invention to provide an improved semiconductor integrated circuit device comprising at least one zener diode and an RC network.
It is still another object of the present invention to provide an improved semiconductor integrated circuit device comprising at least one zener diode located within a semiconductor substrate and an RC network wherein all of those active and passive devices are electrically connected on a front or top side of the semiconductor substrate and a fabrication method therefor.
BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENT
In accordance with one embodiment of the present invention, a semiconductor integrated circuit device is provided which comprises, in combination, a semiconductor substrate; at least one zener diode located in the semiconductor substrate; a capacitor having two electrodes including a semiconductor electrode located in the semiconductor substrate; one level of a metallization layer located on the semiconductor substrate and having one portion providing the other electrode of the two electrodes of the capacitor and at least one other portion providing electrical contact to one portion of the at least one zener diode; an insulating layer located on at least a portion of a top surface of the one level of a metallization layer; a layer of resistive material located on a top surface portion of the dielectric layer; and a second level of a metallization layer located on at least portions of a top surface of the layer of resistive material, the second level of a metallization layer providing a pair of spaced apart metal contacts to the layer of resistive material which together with the layer of resistive material comprises a resistor.
In accordance with another embodiment of the present invention, a method of forming a semiconductor integrated circuit device comprises the steps of providing a semiconductor substrate; forming at least one zener diode located in the semiconductor substrate; forming a capacitor having two electrodes including a semiconductor electrode located in the semiconductor substrate; forming one level of a metallization layer located on the semiconductor substrate and having one portion providing the other electrode of the two electrodes of the capacitor and at least one other portion providing electrical contact to one portion of the at least one zener diode; forming an insulating layer located on at least a portion of a top surface of the one level of a metallization layer; forming a layer of resistive material located on a top surface portion of the dielectric layer; and forming a second level of a metallization layer located on at least portions of a top surface of the layer of resistive material, the second level of a metallization layer providing a pair of spaced apart metal contacts to the layer of resistive material which together with the layer of resistive material comprises a resistor.
The foregoing and other objects, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiments of the invention, as illustrated in the accompanying drawings.
REFERENCES:
patent: 4853759 (1989-08-01), Hague
patent: 5218222 (1993-06-01), Roberts
patent: 5227012 (1993-07-01), Brandli et al.
patent: 5241213 (1993-08-01), Hull
patent: 5355014 (1994-10-01), Rao et al.
patent: 5668384 (1997-09-01), Murakami
patent: 5760450 (1998-06-01), Hurkx et al.
patent: 5770886 (1998-06-01), Rao et al.
patent: 352058382 (1977-05-01), None
patent: 355036941 (1980-03-01), None
patent: 355068669 (1980-05-01), None
patent: 357045283 (1982-03-01), None
patent: 62-58868 (1987-03-01), None
patent: 401145874 (1989-06-01), None
patent: 404127574 (1992-04-01), None
Kravtchenko Dmitri G.
Paderin Anatoly U.
Mintel William
Moy Jeffrey D.
Weiss & Moy P.C.
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