Computer graphics processing and selective visual display system – Computer graphics processing – Three-dimension
Reexamination Certificate
1999-07-26
2002-09-10
Zimmerman, Mark (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics processing
Three-dimension
Reexamination Certificate
active
06448967
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a display memory system to enhance 3D graphics performance, more particularly to a method for reducing memory access of texture mapping, scissor test, alpha test, stencil test, and depth test in a three-dimensional image.
BACKGROUND OF THE INVENTION
As is well known, a typical graphics. display system includes a processor, a frame buffer memory and a display monitor. The frame buffer memory stores digital data which include pixel information such as R, G, B, A value, depth(Z) value and texture images, etc. R, G, B values are the Red, Green, and Blue colors of every position (pixel) on a display and are read out to produce a full screen image. ‘A’ is referred to as Alpha value, which defines the transparency of every pixel. Depths or Z values define the depth of a three-dimensional image and are stored in a buffer memory referred to as a Z-Buffer, which is associated with the frame buffer. Texture images are stored in a buffer memory referred to as a texture memory, which is associated with the frame buffer. Texture images are applied to a three-dimensional image to produce a more realistic image. All of the information in each frame is read out and written in a frame buffer. Thus, the memory bandwidth limits the performance of the system.
Typically, in order to produce realistic three-dimensional images, every pixel may be reprocessed by a texture mapping, a scissor test, an alpha test, a stencil test and a followed Z-Buffer depth test. The texture mapping is a process to read the texture images from a texture buffer, choose the desired pixels from these images and then apply to each pixel. One texture mapped pixel may require one, two, four or eight pixels from different resolution texture images depending on various image qualities. These different resolution texture images are stored in texture memories in different locations. Thus, the texture mapping process usually causes random address accesses which have longer response time than continuous address accesses when using a typical memory. After the texture mapping, there may be other tests, for example: scissor test, alpha test and stencil test, depending on applications. Final test is the Z-Buffer depth test. Z-Buffer depth test is to compare the incoming pixel's depth value with the previous depth value stored in a Z-Buffer. This test is to read the previous depth value in the Z-Buffer, comparing it with new depth value to see whether this new pixel is in front of the pixel being displayed. If the test succeeds, then the new depth value is written to the Z-Buffer, and if the test fails, then this pixel is discarded. Z-Buffer test includes read/compare/write operations. Due to the long latency of memory response and the high frequent request of the texture memory, scissor test, alpha rest, stencil test and Z-Buffer, memory bandwidth is usually not sufficient to support a high performance display system. In order to improve the performance of a display system, the read and write requests of texture memory, alpha test, stencil test and Z-Buffer memory should be reduced.
SUMMARY OF THE INVENTION
In order to overcome the bottleneck problem about the memory, if we can discard those pixels which are in back of the present pixels, then we can reduce the memory access. The present invention provides a method to reduce the memory access of texture mapping, scissor test, alpha test and stencil test. This invention includes two caches, one cache is “Pre-Test Z Cache” which stores the depth(Z) value for Z pre-test stage from the texture mapping and the other cache is a “Z Buffer Cache” which stores Z(depth) values and writes Z value back to the frame buffer. In order to preserve the depth order, the Pre-Test Z Cache and Z Buffer Cache are “first in first out” memory.
The depth value is fetched before texture mapping and stored in Pre-Test Z Cache. The Z pre-test is performed before texture mapping, alpha test, stencil text and Z-Buffer test. The pixel is discarded if it fails in Z pre-test and then the followed memory access is eliminated.
REFERENCES:
patent: 5596686 (1997-01-01), Duluk, Jr.
patent: 6154223 (2000-11-01), Baldwin
Sealey Lance W.
Silicon Integrated Systems Corp.
Zimmerman Mark
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