Computer graphics processing and selective visual display system – Computer graphics processing – Three-dimension
Reexamination Certificate
2000-06-20
2001-08-07
Zimmerman, Mark (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics processing
Three-dimension
C345S426000
Reexamination Certificate
active
06271851
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and system for deleting invalid pixels in a 3D computer graphic processing, especially relates to a method and system for deleting invalid pixels in a 3D computer graphic processing by comparing the depth values of the pixels stored in cache memories which satisfy a Z Test Mode with the depth values of input pixels being processed.
2. Description of the Related Art
Referring to
FIG. 1
, the Z-buffer pre-test system for 3D graphic performance enhancement disclosed in U.S. Ser. No. 09/360,597, which was filed by the applicant, comprises a FIFO
7
, a pre-test Z cache
11
, a Pre-test Z module
8
, a validity-test module
9
, a Z-buffer cache
14
, a Z-buffer test module
10
, a frame buffer memory
13
and a control logic
6
. The FIFO
7
is used to store the input pixels being processed. The pre-test Z cache
11
is used to store the depth values of all pixels having been inputted according to a Z Test Mode. The pre-test Z module
8
is used to compare the depth values of input pixels being processed with the depth values stored in the pre-test Z cache
11
according to the Z Test Mode. If the answer is yes, the content of the pre-test Z cache is updated. If the answer is no, the input pixels are discarded. The validity-test module
9
is used to process a series of tests, such as a scissor test for determining if an input pixel being processed is inside or outside a view port on the screen, such as an alpha test for comparing the alpha value of an input pixel being processed with the predefined alpha value of the system to determine if the input pixel should be discarded, such as a stencil test for comparing a reference value of an input pixel being processed with a parameter stored in a stencil buffer modified by instructions to determine if the input pixel being processed should be discarded. The Z-buffer cache
14
is used to store the depth values of all pixels having been inputted according to the Z Test Mode. The Z-buffer test module
10
is used to compare the depth values of input pixels being processed with the content of the Z-buffer cache
14
according to the Z Test Mode. If the answer is yes, the Z-buffer cache
14
is updated. If the answer is no, the input pixel being processed is discarded. The frame buffer memory
13
is used to store all pixels having passed validity tests. The validity tests include all functions of a depth test, scissor test, alpha test and stencil test mentioned above. The control logic
6
can further comprise a state machine
12
for managing the operations of all components simultaneously.
The original application can be further improved to meet all needs of a 3D computer graphic system. For example, there is a shading process for generating smooth colors in a 3D image processing. The shading process will generate a plurality of parallel input pixels simultaneously. Under the circumstance, the original application will slow down the executing speed if using a sequential process for the plurality of parallel input pixels.
SUMMARY OF THIS INVENTION
The object of the present invention is to eliminate the drawback of slow executing speed for a plurality of parallel input pixels in original application. To this end, the present invention provides a method and system which process the parallel input pixels by a plurality of pre-test units in advance. The plurality of pre-test units are used to compare the depth values of input pixels with the depth values stored in the pre-test Z cache according to a Z Test Mode. If the answer is yes, the input pixels pass and are displayed later. Otherwise, the input pixels are discarded. The Z Test Mode has eight kinds of practical applications, that are “never pass”, “if Z
new
>Z
dst
then pass”, “if Z
new
≧Z
dst
then pass”, “if Z
new
=Z
dst
then pass”, “if Z
new
≠Z
dst
then pass”, “if Z
new
<Z
dst
then pass”, “if Z
new
≦Z
dst
then pass” and “all pass”, wherein Z
new
is the depth value of the input pixel being processed, Z
dst
is the depth value of the pixel having been inputted which is stored in the pre-test Z cache.
In one aspect, the present invention mainly comprises steps (a) to (c) and is used to enhance the performance of a three-dimensional graphic system. The three-dimensional graphic system includes a pre-test Z cache, a pre-test Z module, a control logic, a Z-buffer cache and a frame buffer memory. The pre-test Z cache and Z-buffer cache store depth values of all pixels having been inputted which satisfy the Z Test Mode. In step (a), it is determined if input pixels being processed are in said pre-test Z cache and Z-buffer cache. In step (b), the operations of said frame buffer memory, pre-test Z cache and Z-buffer cache are controlled by said control logic according to the results of step (a). In step (c), the depth values stored in said pre-test Z cache are compared with the depth values of the input pixels being processed by said pre-test Z module. If the comparing result does not satisfy the Z Test Mode, the input pixels are discarded. Otherwise, the depth values of the input pixels being processed are written to the pre-test Z cache.
In another aspect, the present invention mainly comprises a FIFO, a pre-test Z cache, a pre-test Z module, a validity-test module, a Z-buffer cache, a Z-buffer test module, a frame buffer memory and a control logic. The FIFO is used to store a plurality of input pixels being processed. The pre-test Z cache is used to store depth values of all pixels having been inputted which satisfy the Z Test Mode. The pre-test Z module, including a plurality of pre-test units, is used to compare the depth values of the input pixels at the output end of the FIFO with the depth values stored in the pre-test Z cache. If the comparing result does not satisfy the Z Test Mode, the input pixels are discarded. Otherwise, the depth values of the input pixels being processed are written to the pre-test Z cache. The validity-test module, connected to the plurality of pre-test units, is used to execute validity-test functions for the input pixels being processed. The Z-buffer cache, connected to the pre-test Z cache, is used to store the depth values of input pixels having been inputted which satisfy the Z Test Mode. The Z-buffer test module, connected to the Z-buffer cache and validity-test module, is used to compare the depth values of pixels passing through said validity-test module with the depth values stored in the pre-test Z cache. If the comparing result does not satisfy the Z Test Mode, the input pixels are discarded. Otherwise, the depth values of the input pixels are written to the pre-test Z cache. The frame buffer memory, connected to said Z-buffer cache, pre-test Z cache and validity-test module, is used to store all pixels having passed through validity tests. The control logic is used to manage operations of said FIFO, pre-test Z cache, Z-buffer cache and frame buffer memory. The improvement resides in that said pre-test Z module includes a plurality of pre-test units, which compare the depth values stored in said pre-test Z cache with the depth values of the input pixels being processed in a parallel manner to enhance the efficiency of said graphic system.
The present invention can also be implemented by software. Because of simplicity and less operations of the structure of the present invention, the implementation by software also has the advantage as above-mentioned.
REFERENCES:
patent: 4961153 (1990-10-01), Fredricson et al.
patent: 5596686 (1997-01-01), Duluk, Jr.
patent: 5760780 (1998-06-01), Larson et al.
patent: 5870097 (1999-02-01), Snyder et al.
patent: 5914721 (1999-06-01), Lim
patent: 6094200 (2000-07-01), Oslen et al.
Hsiao Chien-Chung
Lee Tsung-Feng
Ladas & Parry
Santiago Enrique L
Silicon Integrated Systems Corporation
Zimmerman Mark
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