Yield surface modeling methodology

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G06F 1700

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active

054385270

ABSTRACT:
A method for predicting yields for integrated circuit designs for given specification limits and process variations with respect to transistor parametric variations is based on a stastical analysis starting with response surface modeling techniques that relate desired circuit outcomes as a function of a set of defined independent variables. The response surfaces are converted to discrete C.sub.pk surfaces for all combinations of the independent variables. The C.sub.pk surfaces are next converted to discrete percent yield surfaces for each of the circuit outcomes which then are combined to provide a composite yield surface comprising all desired parametric operating points of the outcomes that may be used to predict the circuit yield.

REFERENCES:
patent: 3751647 (1973-08-01), Maeder et al.
patent: 5067101 (1991-11-01), Kunikiyo et al.
patent: 5070469 (1991-12-01), Kunikiyo et al.
Hacever et al; "Parametric Yield Optimization For MOS Circuit Blocks"; IEEE CAD 1988.
Alvarez; "Application of Statistical Design and Response Surface Methods to Computer-Aided VLSI device Design"; IEEE CAD 1988.

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