Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
1999-07-19
2001-02-20
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000, C438S253000, C438S618000
Reexamination Certificate
active
06190926
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of integrated circuit processing techniques. More particularly, the present invention relates to a yield enhancement technique of particular utility with respect to the fabrication, processing and packaging of ceramic dual in-line package (“CERDIP”) integrated circuit devices including semiconductor memories such as ferroelectric random access memory devices exemplified by the FRAM® family of integrated circuit devices available from Ramtron International Corporation, Colorado Springs, Colo., assignee of the present invention.
The absorption of moisture (H
2
O) into certain chemical vapor deposition (“CVD”) deposited silicon dioxide (SiO
2
) and glass film dielectrics is a well known phenomenon with the presence of the H
2
O content being reasonably deduced by analysis of the stress vs. temperature characteristics of the films. When subjected to temperatures above 200° Celsius (“C”) in subsequent wafer processing, the H
2
O contamination is also known to diffuse out of the dielectric films and react with adjacent metals such as aluminum (Al) and titanium nitride (TiN) to form a metal oxide with a reaction byproduct of hydrogen (i.e. 3H
2
O+2Al=Al
2
O
3
+3H
2
). This absorption and subsequent release of moisture is also known to cause instability problems for standard MOS and CMOS semiconductor and integrated circuit devices through aluminum corrosion, contact “poisoning”, undesirable “hot carrier” effects, increased leakage currents, threshold voltage (“Vt”) shifts, increased metal resistivity and the like. The destructive effects of H
2
on switching performance of ferroelectric integrated circuit memory devices is also known.
Ferroelectric memory devices, such as the FRAM® family of integrated circuit devices, provide non-volatile data storage through the use of a ferroelectric dielectric material which may be polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within the Perovskite crystals in the dielectric material. This alignment may be selectively achieved by application of an electric field which exceeds the coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles.
A hysteresis curve, wherein the abscissa and ordinate represent the applied voltage (“V”) and resulting polarization (“Q”) states respectively, may be plotted to represent the response of the polarization of a ferroelectric capacitor to the applied voltage. A more complete description of this characteristic hysteresis curve is disclosed, for example, in U.S. Pat. Nos. 4,914,627 and 4,888,733 assigned to the assignee of the present invention, the disclosures of which are herein specifically incorporated by this reference.
Data stored in a ferroelectric memory cell is “read” by applying an electric field to the cell capacitor. If the field is applied in a direction to switch the internal dipoles, more charge will be moved than if the dipoles are not reversed. As a result, sense amplifiers can measure the charge applied to the cell bit lines and produce either a logic “1” or “0” at the IC output pins provided that Q is sufficiently large. In a conventional two transistor/two capacitor (“2T/2C”) ferroelectric memory cell, a pair of two data storage elements are utilized, each polarized in opposite directions. To “read” the state of a 2T/2C memory cell, both elements are polarized in the same direction and the sense amps measure the difference between the amount of charge transferred from the cells to a pair of complementary bit lines. In either case, since a “read” to a ferroelectric memory is a destructive operation, the correct data is then restored to the cell.
Ferroelectric memory cell structures are disclosed in the following U.S. Pat. No. 4,873,664 issued Oct. 10, 1989 for “Self-Restoring Ferroelectric Memory”; U.S. Pat. No. 5,381,364 issued Jan. 10, 1995 for “Ferroelectric-Based RAM Sensing Scheme Including Bit-Line Capacitance Isolation”; U.S. Pat. No. 5,525,528 issued Jun. 11, 1996 for “Ferroelectric Capacitor Renewal Method”; U.S. Pat. No. 5,530,668 issued Jun. 25, 1996 for “Ferroelectric Memory Sensing Scheme Using Bit Lines Precharged to a Logic One Voltage” and U.S. Pat. No. 5,532,953 issued Jul. 2, 1996 for “Ferroelectric Memory Sensing Method Using Distinct Read and Write Voltages”, all assigned to Ramtron International Corporation, Colorado Springs, Colo., assignee of the present invention, the disclosures of which are herein specifically incorporated by this reference.
In a simple “write” operation, an electric field is applied to the cell capacitor to polarize it to the desired state. Briefly, the conventional write mechanism for a 2T/2C memory cell includes inverting the dipoles on one cell capacitor and holding the electrode, or plate, to a positive potential greater than the coercive voltage for a nominal 100 nanosecond (“nsec.”) time period. The electrode is then brought back to circuit ground for the other cell capacitor to be written for an additional nominal 100 nsec. In any event, the switching polarization (“Q
SW
”) of the device must be sufficiently large for the signal presented to the sense amplifiers to be accurately read and the performance of the device is severely degraded should Q
SW
be too low for reliable operation.
As previously stated, ferroelectric random access memory devices are known to be especially sensitive to the aforedescribed out-diffusion of hydrogen and it is believed that this may exacerbate, at least in part, the relatively poor adhesion characteristics exhibited at the interface between platinum (Pt) and certain ferroelectric dielectrics such as Ramtron International Corporation's proprietary lead zirconate titanate (“PZT”) films. This mechanism is currently believed to be the cause of an observed Q
SW
switching degradation, particularly following CERDIP packaging or other packaging or processing steps requiring a 440° Celsius annealing step. In some cases, yields of little more than 0% have been encountered which is believed to be most probably due to the outgassing of moisture and/or hydrogen.
SUMMARY OF THE INVENTION
A yield enhancement technique for integrated circuit processing is disclosed herein which reduces the deleterious effects of any moisture contamination which might be absorbed by conventional dielectric films and thereafter result in an undesired out-diffusion of hydrogen when the integrated circuit die is subsequently subjected to relatively high processing temperatures such as those experienced in CERDIP packaging. The technique disclosed comprises the formation of an interlevel dielectric layer having hydrophilic (or moisture absorbing) properties (for example, SiO
2
deposited using 7.5% phosphorus doped tetraethyloxysilicate “PTEOS”) at least partially surrounding a device on the integrated circuit which layer is then subjected to an annealing operation to drive off at least a portion of any moisture present therein. A second relatively less hydrophilic dielectric layer (such as SiO
2
deposited using undoped tetraethyloxysilicate “UTEOS”) is then overlaid in at least partial communication with the interlevel dielectric layer and an overlying passivation layer (such as UTEOS) is then applied to the integrated circuit prior to completion of the integrated circuit processing and subsequent packaging operations.
As presently understood, the annealed hydrophilic layer functions as a “getter” for out-diffusion from subsequent unannealed dielectric layers and the higher the phosphorus content of the hydrophilic layer, the higher its saturation for moisture. The subsequent relatively less hydrophilic dielectric and passivation layers may be formed of UTEOS, (which are not annealed) and will retain much less moisture than PTEOS films.
Particularly disclosed herein is a method for yield enhancement in an integrated ci
Argos, Jr. George
Harper Holli
Mitra Sanjay
Perino Stanley C.
Dang Trung
Hogan & Hartson LLP
Kebede Brook
Kubida, Esq. William J.
Ramtron International Corporation
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