Yield based, in-line defect sampling method

Details Yield based, in-line defect sampling method Yield based, in-line defect sampling method

1998-08-21

2001-07-24

Le, Vu A. (Department: 2824)

Semiconductor device manufacturing: process

With measuring or testing

C438S004000

Reexamination Certificate

active

06265232

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to integrated circuit semiconductor device manufacturing. More particularly, the instant invention pertains to methods for integrated circuit defect detection, classification, and review in the wafer stage of the integrated circuit semiconductor device manufacturing process.
2. State of the Art
Integrated circuit semiconductor devices (IC's) are small electronic circuits formed on the surface of a wafer of semiconductor material such as silicon. The IC's are fabricated in plurality in wafer form and tested by a probe to determine electronic characteristics applicable to the intended use of the IC's. The wafer is then subdivided into discrete IC chips or dice, and then further tested and assembled for customer use through various well-known individual die IC testing and packaging techniques, including lead frame packaging, Chip-On-Board (COB) packaging, and flip-chip packaging (FCP) Depending upon the die and wafer sizes, each wafer is divided into a few dice or as many as several hundred or more than one thousand discrete dice.
Tests may be conducted at various stages in the manufacturing process The tests generally conducted on packaged IC's are known as pre-grade, burn-in, and final tests, which test IC's for defects and functionality, and grade each IC for speed. Where the probability that a wafer or a wafer lot will yield acceptable IC's is high, tests are typically omitted for most of the IC's and reliance for at least some tests is placed on testing of a relatively small sample of IC's.
The yield in manufacture of IC's is normally limited by defects. Defects may be inherent in the semiconductor material from which a number of wafers are sliced, or may result from any of the manufacturing steps including initial wafer slicing. Defects are generally classified as either “lethal” defects, which will disable an IC, or “benign” defects Benign defects may have various degrees of benignancy. For example, some defects may be tolerated for certain less demanding use of the IC, or the IC or wafer may be reworked relatively easily for satisfactory operability in other applications When any of the wafers in a wafer lot appear to be unreliable because of fabrication or process errors, all of the wafers in the lot typically undergo enhanced reliability testing. A wafer lot may comprise 50 or more wafers, many of which are probably not deemed to be unreliable Thus, in requiring testing of all wafers, a large waste in test time, labor and expense is incurred.
In addition, IC's which may be initially rejected based on a particular test criterion may be later retested to meet different specifications. Again, test facilities and personnel time are diverted from testing untested IC's to do retesting.
A substantial part of the cost in producing integrated circuits is incurred in testing the devices. Thus, it is important to identify potentially defective IC's as early as possible in the manufacturing process to not only reduce intermediate and final testing costs, but to avoid the other manufacturing expenses in the production of failing IC's. Identification of wafer defects prior to subsequent IC manufacturing steps and extensive testing steps is beneficial in deciding whether the wafer or other wafers in the lot should be used, reworked, or discarded. In addition, under the current test protocol, the initial elimination of potentially defective IC's from the manufacturing process will avoid the necessity of testing large numbers of IC's from other wafers in the same wafer lot.
As described in U.S. Pat. No. 5,301,143 of Ohri et al., U.S. Pat. No. 5,294,812 of Hashimoto et al., and U.S. Pat. No. 5,103,166 of Jeon et al., some methods have been devised to electronically identify individual IC's. Such methods take place “off” the manufacturing line, and involve the use of electrically retrievable identification (ID) codes, such as so-called “fuse-ID's” which are programmed into individual IC's for identification The programming of a fuse-ID typically involves selectively blowing an arrangement of fuses and anti-fuses in an IC so that when accessed, an ID code for the particular IC is outputted. Unfortunately, none of these methods addresses the problems of identifying those IC's on a manufacturing line which will probably fail during subsequent testing and processing, and identifying wafers which will probably have an unacceptable failure rate, i.e., yield loss.
Various apparatus have been devised for locating, identifying, and microscopically examining surface defects on semiconductor wafers, LCD's and the like. Such equipment is disclosed, for example, in U.S. Pat. No. 5,127,726 of Moran, U.S. Pat. No. 5,544,256 of Brecher et al., and U.S. Pat. No. 4,376,583 of Alford et al.
Commercially available wafer scanning tools are made by KLA Instruments Corporation of Santa Clara, Calif., Tencor Instruments Corporation of Mountain View, Calif., Inspex, Inc. of Billerica, Mass., and other companies.
In an attempt to determine when a defect or defects may be lethal or killing to the purpose of an IC, defects have been classified by size, e.g. “large area defects” and “point defects”, and by the number of defects in a statistically generated “cluster” of defects In addition, defects may be further classified by type or cause, e.g. incomplete etch, stacking faults, slip, dislocations, particle contamination, pinholes (intrusions), bridges (protrusions), etc.
U.S. Pat. No. 5,539,752 of Berezin et al. discloses a method for automated defect analysis of semiconductor wafers, using available wafer scanning tools. Defects from different sub-populations are initially preclassified by type, so that subsequent counts of each type on wafers will provide numbers of each type to provide warnings regarding particular manufacturing steps.
In U.S. Pat. No. 5,240,866 of Friedman et al., a method for characterizing circuit defects in a wafer is based on detecting clustering of defects to find a common cause.
Automatic defect detection and sampling is discussed in S. L. Riley, Optical Inspection of Wafers Using Large-Area Defect Detection and Sampling, IEEE Computer Society Press, 1992, pp 12-21. The proposed algorithm relies on the detection of clustered chips and selects defects for sampling on the basis of clustering, without considering defect size or the predicted effect on yield.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to a method for identifying integrated circuit defects at the wafer stage and classifying the identified defects in accordance with the predicted potential for causing losses in yield, whereby measures may be taken in-line to correct or ameliorate the losses, a method for identifying wafer defects having the greatest predicted effect on yield loss, whereby in-line corrective measures are directed at the defects which affect wafer yield to the greatest degree, and such methods which may be carried out with the use of a computer.
The invention relates to the identification of semiconductor wafers having the greatest predictive yield loss so that the reasons for such yield loss may be addressed in-line. The method of processing includes surface inspection to determine defects on the wafer wherein defects are classified in a computer generated file by numbers, locations, ranges of sizes, defect types and the particular die or dice affected thereby.
In an algorithm of the invention, a die yield loss value DYL is calculated for each die of the wafer; the DYL values are summed to obtain a wafer yield loss value WYL. The effect of each size range of defect upon wafer yield loss WYL may then be calculated.
Defects may then be randomly selected from each defect size range for engineering review, whereby in-line changes may be made to the production process to reduce the numbers or effects of defects most affecting the wafer yield.
Thus, the method permits the defects having the greatest yield limitin

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