X-ray inspection of ball contacts and internal vias

Details X-ray inspection of ball contacts and internal vias X-ray inspection of ball contacts and internal vias

2000-10-03

2002-08-27

Kim, Robert H. (Department: 2882)

X-ray or gamma ray systems or devices

Specific application

Absorption

C438S016000

Reexamination Certificate

active

06442234

ABSTRACT:

RELATED APPLICATIONS
This application contains subject matter similar to that disclosed in U.S. patent application Ser. No. 09/661,038, filed on Sep. 13, 2000.
FIELD OF THE INVENTION
The present invention relates to a method for performing inspection and analysis of electrical contacts and associated vias of electrical devices. More particularly, the present invention pertains to an improved method of inspection using X-ray analysis of flip-chip connection and/or ball grid contact arrays (“BGA”) and their associated internal vias, such as are utilized in semiconductor integrated circuit (“IC”) devices and circuit boards therefor, for determination of offset or misalignment, voids, and layer separation (i.e., delamination).
BACKGROUND OF THE INVENTION
An increasingly important aspect of semiconductor IC manufacturing technology is mounting of the semiconductor IC chip or die to an appropriate substrate. Frequently, this requires providing the chip or die with as many input/output (“I/O”) terminals as is possible. As a consequence of the requirement for a large number of terminals to be formed on a limited amount of chip or die surface, so called “flip-chip” structures and bonding techniques have been developed in order to provide high a real density interconnections between the IC chip or die and the substrate.
According to flip-chip methodology, the IC chip or die is mounted via direct bonding to a substrate, e.g., an integrated circuit package such as a printed circuit board or a ceramic circuit board (“IC package”). Generally, the flip-chip process entails disposing a plurality of raised and embedded contacts, e.g., in the form of solder balls or bumps, on the upper major surface of the chip or die (termed a ball grid array, “BGA”), wherein the solder balls or bumps may overlie and connect with internal vias of the IC device. The IC chip or die is then “flipped” over so that the solder balls or bumps face and are mated with a corresponding ball grid array (BGA) or bonding pads on the substrate surface, which BGA or bonding pads may also overlie and electrically contact internal vias of the substrate for electrically connecting underlying metallization levels, patterns, etc. Once mated, the solder bumps or balls of the IC die or chip and the corresponding solder bumps or balls or bonding pads of the substrate are heated to effect reflow and mutual bonding, whereby each solder ball or bump forms a bond between the chip or die and the substrate. As a consequence, each bonded combination functions as both an electrical and physical contact.
According to flip-chip methodology, electrically conductive balls or bumps comprising a solder material are formed on the IC chip or die, as well as on the mating surface of the substrate. Bonding between the two sets of solder balls or bumps is effected by application of heat to the chip or die and the substrate. The application of heat causes both sets of solder-based balls or bumps to reflow, thereby providing physical and ohmic connection therebetween, causing the mated pairs of solder-based wetted balls or bumps to at least partially collapse. Often, a “pancake” shape is created which advantageously reduces interconnection length and resistance.
Flip-chip contact arrangements, such as described above, are susceptible to exhibiting poor ohmic contact performance and/or poor physical bonding, in extreme instances leading to device failure. Poor ohmic resistance and/or poor physical bonding may result from a number of factors, including, inter alia, offset or misalignment of the solder ball or bump forming the external, raised contact, and the underlying internal via structure; presence of voids in the ball/via structure, whether arising during manufacture or subsequent thereto as a result of, e.g., electromigration of one or more metallic elements or components thereof; and layer separation, i.e., delamination, disbonding, or oxidation of the surfaces of e.g., the solder ball or bump and the underlying via due to compositional differences which result in poor mutual adhesion.
As a consequence of the above-described several possible, but distinct, scenarios or mechanisms leading to poor performance of BGA and flip-chip contact/via structures, inspection and/or failure analysis is generally necessary for determining the particular mechanism responsible for poor performance or failure of a particular device or component. However, methodology for performing simple, reliable, and rapid sample preparation for visual or X-ray failure analysis and/or inspection of a particular area-of-interest (AOI) of a BGA or flip-chip array with associated underlying vias is presently unavailable. Moreover, a convenient method for performing high magnification, visual and/or X-ray inspection and/or analysis of an AOI of a BGA or flip-chip array of either or both of a semiconductor IC chip or die and circuit board or IC package therefor, is similarly presently unavailable.
Accordingly, there exists a need for improved methodology for simple, reliable, and rapid X-ray inspection and/or analysis of solder ball/underlying via structures of a particular AOI of a semiconductor IC chip or die or circuit board therefor, which methodology is capable of revealing all pertinent internal structural features e.g., flip-chip devices and contacts, and does not require costly, specialized, or customized equipment or apparatus.
The present invention, wherein a particular AOI of a BGA or flip-chip array of solder ball contacts/underlying vias of an IC die or chip or circuit board therefor is isolated and removed therefrom and mounted on a transparent substrate, which in turn is held by a rotatable gripping means, e.g., a rotatable and tiltable chuck, thereby facilitating performing visual and/or X-ray transmission inspection and/or analysis at high magnification levels, effectively addresses the need for improved methodology for performing failure analysis leading to development of improved, low ohmic resistance, well-aligned, void-free, adherent ball contact/underlying via structures. Further, the means and methodology provided by the present invention enjoy diverse utility in the manufacture of numerous and various types of electrical and electronic devices and/or components utilizing ball contact/via combinations.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is an improved method for simple, reliable, and rapid, X-ray radiography inspection and/or analysis at high magnification of raised ball contact/underlying via combinations or structures of electrical components.
Another advantage is an improved method for performing high magnification, X-ray analysis of BGA or flip-chip raised contact/underlying via structures of particular AOI's of semiconductor IC devices and/or printed circuit board or ceramic circuit board.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized as particularly pointed out in the appended claims.
According to one aspect of the present invention, the foregoing and other advantages are obtained in part by a method for performing inspection and/or analysis of raised and embedded electrical contacts and associated underlying vias of an electrical component having opposing first and second major surfaces, the first major surface including an array of closely spaced-apart raised electrical contacts with respective underlying vias.
Within an electrical component, an area-of- interest (“AOI”) comprising a row of contacts on said first major surface and respective underlying vias is identified. The AOI, including at least one of the raised electrical contacts with its respective underlying via, is isolated for X-ray imaging. X-ray images of the AOI are created, depicting at least one of the raised and embedded electrical contacts with its respective

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