Image analysis – Applications – Manufacturing or product inspection
Reexamination Certificate
2000-10-05
2004-12-21
Mehta, Bhavesh M. (Department: 2625)
Image analysis
Applications
Manufacturing or product inspection
C382S145000, C438S016000, C438S017000, C250S370010
Reexamination Certificate
active
06834117
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
This invention is in the field of integrated circuit manufacturing, and is more specifically directed to the non-destructive detection of defects in metal conductors of integrated circuits.
A critical step in the manufacture of integrated circuits is the formation of metal a conductors. Upper levels of conductors in integrated circuits are typically formed of copper or aluminum metallization, in order to bear the relatively high currents required in the distribution of power in the integrated circuit. As is known in the art, an upper current density limit for metal conductors is set to a level that avoids electromigration and other current-dependent voiding. This limit typically determines the minimum line width for the conductors in the integrated circuit, which is often a major factor upon which the overall integrated circuit chip area depends. In order to minimize the chip area required for realization of complex integrated circuits such as digital signal processors (DSPs) or microprocessors, multiple metallization levels are now quite common in the art, despite the complex manufacturing processing required for their fabrication.
Voiding in metal conductors is an important defect that can occur in the fabrication of thin, closely-spaced, metal conductors, particularly in multiple layers. Voids may be caused in the deposition of the metal film, as a result of metal etch, or by unintended corrosion during processing. Voids can also be caused by migration of atoms during thermal processing, or due to electrical stress; voids in metal conductors can also be present because of the inability of large grains to fill gaps, particularly in small geometries and over topography. Because of the yield loss due to defective metal lines, and also considering later-life reliability hazards resulting from the increased current density borne by a conductor in the locality of a void, the prevention of voids in metal conductors is of extreme importance in modern integrated circuit manufacturing.
In previous years, metal voids could be readily detected by visual inspection of the integrated circuits during or after their manufacture. Additionally, the reduction in metal conductors to the sub-micron range has not only reduced the optical visibility of the conductors, but has also increased the number of conductors that may be formed in a given chip area, eliminating the practicality of such visual inspection, even on a meaningful spot-check basis. This reduction in feature size has also reduced the minimum size of a killing void further below the visibility of optical microscopy. In addition, the presence of voids within the body of a conductor line cannot be detected by visual or scanning electron microscopy (SEM) techniques that are currently in use. Particularly in damascene copper structures, voids are typically buried in this manner, and are thus optically invisible, regardless of the conductor dimensions. The implementation of multiple metal levels has also limited visual inspection, because the opacity of the upper metal levels prevents top-side visual inspection of underlying metal conductors.
As a result, conventional inspection techniques now rely upon destructive techniques. Typically, sample wafers from the manufacturing line are cross-sectioned, and the cross-sections are examined by SEM for a measure of the metal film quality. The destructive nature of this inspection of course minimizes the number of samples that may be inspected by SEM. Furthermore, the nature of SEM precludes the viewing of more than a small number of locations of the wafer within each sample. The preparation of the cross-sectional samples for SEM analysis is also time-consuming, and thus costly. As such, routine SEM inspection is not a very effective measure of the metallization film quality.
Other techniques for measuring the quality of metallization films have been reported as under development. Magnetic force microscopy measures variations in magnetic flux caused by voids in the metallization; of course, this measurement not only requires current to be conducted through the conductor during measurement, but also highly precise magnetic field detection elements. Surface acoustic wave (SAW) microscopy has also been proposed, in which variations in reflection of acoustic waves due to voids may be measured, but resolution considerations tend to limit the applicability of SAW microscopy to small geometries.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a non-destructive method of inspecting the quality of small-geometry metallization in integrated circuits.
It is a further object of the present invention to provide such a method in which the inspection technique directly relates to, the film construction, such as by way of differential absorption of incident electromagnetic radiation.
It is a further object of the present invention to provide such a method in which large portions of the integrated circuit maybe efficiently inspected, so as to be performable in-line.
It is a further object of the present invention to provide such a method in which metallization voids may be distinguished from particles in the film.
It is a further object of the present invention to provide such a method in which the results from the inspection may readily be correlated to visually apparent film defects, such as scratches and larger particles.
It is a further object of the present invention to provide such a method in which the wafer inspection maybe carried out in a non-contact manner.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.
The present invention may be implemented into an apparatus and method for inspecting integrated circuit wafers at various stages of manufacture, particularly after the formation of one or more layers of metallization (typically copper or aluminum), patterned into metal conductors. Inspection is carried out by exposing the wafer to locally focused x-ray energy, through submicron apertures in an exposure array that is otherwise opaque to x-rays. A detector array is disposed on the opposite side of the wafer, having apertures therein that are physically registered to the apertures of the exposure array. The detector array spatially indicates the locations at which transmitted x-ray energy passes through the wafer; these indications can be used to identify the location of voids or other defects in the overlying metallization. Repeated exposures in combination with indexing of the wafer relative to the exposure and receiving apertures, effectively scans the wafer. Image processing or other signal analysis can be applied, resulting in a viewable image of the wafer or alternatively in the automated detection and differentiation of voids and other defects.
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Chatterjee Basab
Guldi Richard L.
Rao Satyavolu Papa
Bayat Ali
Brady III W. James
Garner Jacqueline J.
Mehta Bhavesh M.
Telecky , Jr. Frederick J.
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