X-cell EEPROM array

Details X-cell EEPROM array X-cell EEPROM array

1987-12-16

1989-06-13

Larkins, William D.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 41, 357 45, 365185, H01L 2704, H01L 2978, G11C 1140

Patent

active

048397059

ABSTRACT:
An X-cell EEPROM array includes a plurality of common source regions (50) that each border on four gate regions (46), both formed at a face of a semiconductor substrate (10). Each gate region (46) further adjoins a common drain region (52). Each drain region (52) is a common drain for two EEPROM select and memory transistors. A common erase region (54) is implanted into the semiconductor layer (10) in a position remote from the source regions (50) and the drain regions (52). Four floating gate electrodes (40) extend over tunnel windows (22) that are formed on the semiconductor layer (10) in positions adjacent a single erase region (54). An integral contact (64) is made through multilevel oxide (56, 58) from a metal erase line (70) to each erase region (54).

REFERENCES:
patent: 4209849 (1980-06-01), Schrenk
patent: 4281397 (1981-07-01), Neal et al.
patent: 4288863 (1981-09-01), Adam
patent: 4603341 (1986-07-01), Bertin et al.

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