Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2006-09-12
2006-09-12
Le, Thong Q. (Department: 2827)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S194000, C365S230010
Reexamination Certificate
active
07106648
ABSTRACT:
The disclosed is a memory such DRAM (dynamic random access memory), particularly an X-address extractor, an X-address extraction method and a memory adaptable to a high speed operation. A DRAM receives X and Y-addresses through an address line. The X-address is input through a command line when an active command is input to the DRAM, and the Y-address is input when a read/write command is input to the DRAM. The X-address abstractor performs a function of extracting the X-address from the X and Y addresses transferred through the address line. A conventional X-address extractor has a problem that the X-address has a different value when a selection signal changes to logic ‘0’ from logic ‘1’ after an address signal changes to another value from an X-address. The present X-address extractor includes a selection signal generator, a delayer, a latch and an X-address switch, without the problem of the conventional art.
REFERENCES:
patent: 6353572 (2002-03-01), Yagishita
patent: 6552957 (2003-04-01), Yagishita
patent: 6754783 (2004-06-01), Tsern et al.
patent: 6781919 (2004-08-01), Mizuhashi
Hynix / Semiconductor Inc.
Le Thong Q.
Marshall & Gerstein & Borun LLP
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