Writing of instruction results produced by instruction execution

Details Writing of instruction results produced by instruction execution Writing of instruction results produced by instruction execution

1998-11-17

2000-12-19

Treat, William M.

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

712225, G06F 1500

Patent

active

061638374

ABSTRACT:
Two instruction executions circuits C1 and C2, possibly pipelined, share a write port to write instruction results to their destinations. When both circuits have results available for writing in the same clock cycle, the write port is given to circuit C1. Circuit C2 gets the write port only when there is a bubble in the write back stage of circuit C1. Circuit C2 executes instructions that occur infrequently in an average program. Examples are division, reciprocal square root, and power computation instructions. Circuit C1 executes instructions that occur more frequently. Circuits C1 and C2 are part of a functional unit of a VLIW processor.

REFERENCES:
patent: 3753234 (1973-08-01), Gilbert et al.
patent: 6081783 (2000-06-01), Divine et al.
M. Deering, "Geometry Compression", Computer Graphics Proceedings SIGGRAPH 95 (Aug. 6-11, 1995), pp. 13-20.
E. Angel, "Interactive Computer Graphics: A-Top Down Approach with OpenGL" (1997), pp. 13-20.
J.D. Foley et al., "Computer Graphics: Principles and Practice" (1996).

Affiliated with

Also associated with

Rating

Writing of instruction results produced by instruction execution does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Writing of instruction results produced by instruction execution, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Writing of instruction results produced by instruction execution will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-278032