Writing circuit for non-volatile memory

Details Writing circuit for non-volatile memory Writing circuit for non-volatile memory

1996-06-24

1997-09-09

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular connection

36518514, 36518524, 36518523, B11C 1134

Patent

active

056663080

ABSTRACT:
A writing circuit for non-volatile memory capable of preventing the structure of the circuit from becoming complicated in an integrated circuit from the points of view of logic and layout by reducing the number of kinds of control signal voltages. The circuit includes a first NMOS transistor N1, a first PMOS transistor P1, a second NMOS transistor N2 which serves as a non-volatile memory write terminal and a depression type MOS transistor D1 having a source to which a control signal PGM for controlling the output condition of the above-mentioned write terminal is applied.

REFERENCES:
patent: 5333122 (1994-07-01), Ninomiya
patent: 5392236 (1995-02-01), Hashimoto

Affiliated with

Also associated with

Rating

Writing circuit for non-volatile memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Writing circuit for non-volatile memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Writing circuit for non-volatile memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-74092