Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-06-09
2002-04-16
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
Reexamination Certificate
active
06373326
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a writing circuit, particularly to a writing circuit provided in a semiconductor memory device.
This application is a counterpart of Japanese patent application, Serial No. 165214/1999, filed Jun. 11, 1999, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
FIG. 1
shows a circuit configuration of a nonvolatile memory device having a conventional writing circuit, wherein the nonvolatile memory device comprises a writing circuit
100
and a memory circuit
104
. The writing circuit
100
comprises a writing control circuit
101
, an oscillation circuit
102
connected to the output side of the writing control circuit
101
, and a charge pump circuit
103
connected to the output side of the oscillation circuit
102
. The writing circuit
100
controls the writing operation in the memory circuit
104
using a high voltage VPP generated in the charge pump circuit
103
. The writing control circuit
101
supplies an oscillation instruction signal START representing the start of oscillation to the oscillation circuit
102
. The oscillation circuit
102
supplies a clock CK and an inverted clock CK/ to the charge pump circuit
103
. The charge pump circuit
103
generates the high voltage VPP and supplies the high voltage VPP to the memory circuit
104
.
Described hereinafter is a case where the writing circuit
100
writes data in the memory circuit
104
. The writing control circuit
101
renders the oscillation instruction signal START representing the start of oscillation, namely, “H” (i.e., High). The oscillation circuit
102
oscillates in response to the oscillation instruction signal START so as to generate the clocks CK, CK/, e.g., of 5 MHz, and the two clocks CK, CK/ are supplied to the charge pump circuit
103
. The charge pump circuit
103
boosts a power supply voltage in response to the two clocks CK, CK/ so as to generate the high voltage VPP. If the memory circuit
104
is composed of, e.g., a nonvolatile memory such as an EEPROM, the thus generated high voltage VPP is about 20 volts. The memory circuit
104
writes and stores data therein upon reception of the high voltage VPP. If the memory circuit
104
is composed of the EEPROM, it stores data therein by causing tunneling in an internal memory cell thereof. The thus supplied high voltage VPP is required to have a voltage value not less than a given value (threshold voltage) so that the memory circuit
104
stores data therein. Whereupon, if the high voltage VPP is not more than the threshold voltage (15 volts), the tunneling does not occur so that data is not stored in the EEPROM, i.e., memory circuit
104
.
However, the conventional writing circuit has the following problems.
In the conventional writing circuit, the high voltage VPP generated in the charge pump circuit
103
is not determined. Accordingly, the verification whether a writing operation is effected properly or not is performed by confirming data upon completion of the writing operation.
Further, if the high voltage VPP is unstable (in cases where a voltage is close to threshold voltage), the writing operation is effected or not effected in some cases. Accordingly, there is a possibility that the data written in the memory circuit
104
is corrupted to the extent that it cannot be recovered.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a writing circuit in a semiconductor memory device.
Another object of the invention is to provide a voltage detecting circuit in a writing circuit.
To achieve the above object, charge pump circuit
203
boosts a power supply voltage to generate a high voltage VPP in response to clocks CK, CK/ supplied from an oscillation circuit
202
. A voltage detecting circuit
205
discriminates whether the high voltage VPP reaches a desired voltage value or not and represents it by discrimination signals LVPP, DIS/. If the high voltage VPP does not reach the desired voltage value, a writing control circuit
201
stops the oscillation circuit
202
from effecting its oscillating operation and stops the charge pump circuit
203
from boosting the power supply voltage to the high voltage VPP in response to the discrimination signal DIS/. Accordingly, the high voltage VPP having a desired voltage value is not applied to a memory cell of a memory circuit
204
so that writing is not effected. Further, the discrimination signal LVPP is outputted externally so as to represent the writing state in the memory cell.
REFERENCES:
patent: 5640118 (1997-06-01), Drouot
Oki Electric Industry Co, Ltd.
Rabin & Berdo P.C.
Tra Quan
Tran Toan
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