Write strobe generator for clock synchronized memory

Details Write strobe generator for clock synchronized memory Write strobe generator for clock synchronized memory

1983-01-31

1984-10-09

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307268, 307247R, 307262, 307585, 307601, 307602, 307605, 328 55, 328 61, H03K 386, H03K 506

Patent

active

044764014

ABSTRACT:
An on-chip memory control circuit generates a proper WRITE STROBE signal for a clock synchronized pipe-line operated integrated circuit memory. A symmetrical clock signal having half the frequency of the system clock is produced by applying the system clock to the C input of a standard master slave delay type flip-flop having its Q output fed back to its D input. A negative going pulse train .phi..sub.P comprising a pulse at every transition of the symmetrical clock is generated by a level change detector which issues a pulse of a desired width whenever a level change at its input is detected. A delayed pulse train .phi..sub.PD is produced by delaying .phi..sub.P an amount which depends on the speed of the memory and other design criteria. The pulse drains .phi..sub.P and .phi..sub.PD are applied to an asynchronous flip-flop, the output of which corresponds to the desired WRITE STROBE signal.

REFERENCES:
patent: 3391389 (1968-07-01), Cruger et al.
patent: 3443232 (1969-05-01), Stinson
patent: 3473129 (1969-10-01), Tschannen
patent: 3493884 (1970-02-01), Kulp
patent: 3504288 (1970-03-01), Ross
patent: 4105980 (1978-08-01), Cowardin et al.

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