Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-03-12
2003-09-09
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110, C365S185330
Reexamination Certificate
active
06618291
ABSTRACT:
BACKGROUND OF THE INVENTION
I. Field of the Invention
The present invention relates to the field of nonvolatile memory devices. In particular, the present invention relates to an improved write state machine for flash memory devices.
II. Description of the Related Art
One type of nonvolatile memory is flash electrically erasable programmable read only memory (flash EEPROM, or “flash memory”). Similar to electrically erasable programmable read only memory (EEPROM), flash memory may be erased electrically without being removed from the computer system. Flash memory is also similar to erasable programmable read only memory (EPROM) because flash memory is arranged in blocks such that the entire contents of each block must be erased at once.
Flash memories differ from conventional electrically erasable programmable read only memory (“EEPROMs”) with respect to erasure. Conventional EEPROMs typically use a select transistor for individual byte erase control. Flash memories, on the other hand, typically achieve much higher density with single transistor cells. During one prior art flash memory erase method, a high voltage is supplied to the sources of every memory cell in a memory array simultaneously. This results in a full array erasure.
Conventionally for flash EEPROM, a logical “one” means that few if any electrons are stored on a floating gate associated with a bit cell. A logical “zero” means that many electrons are stored on the floating gate associated with the bit cell. Erasure of this type of flash memory causes a logical one to be stored in each bit cell. Each single bit cell of this type of flash memory cannot be overwritten individually from a logical zero to a logical one without an erasure of an entire block of memory cells. Each single bit cell of that flash memory can, however, be overwritten from a logical one to a logical zero, given that this entails simply adding electrons to a floating gate that contains the intrinsic number of electrons associated with the erased state. The process of adding electrons to the floating gate associated with a bit cell is referred to as programming.
The erasure process of a flash memory array typically involves several steps typically including precondition and postcondition steps. First, the transistors of the block to be erased are preconditioned, whereby the threshold voltages of the memory transistors are increased. The preconditioned transistors are then erased and verified. Certain transistors may have been over-erased, and hence may have negative threshold voltages. These transistors are postconditioned to bring their threshold voltages back up to a certain minimum level. The programming process is similarly comprised of various steps. Flash memory cells are programmed and verified to ensure that programming was successful.
Flash memory has a limited threshold for the number of programming and erasure cycles which each flash memory device can withstand before device degradation or failure. Typically this threshold is about a 100,000 programming and erasure cycles. This cycle lifetime can be further extended to 1,000,000 cycles when flash memory devices incorporate wear-leveling algorithms that distribute data amongst flash memory blocks.
Conventional flash memory devices that do not contain logic to control program and erase sequences burden the system microprocessor with the task of sequencing the flash memory through its program and erase steps. More recent flash memory devices incorporate write state machines which help alleviate the heavy burden on the microprocessor. Upon receipt of a command from the microprocessor, the write state machine cycles the flash memory array through its many erase or program steps automatically, and then reports back to the microprocessor when it is finished.
In previous flash memory devices incorporating a write state machine, the microprocessor could not read from or write to the flash memory device while the erase and program sequences were being performed. The erase and program sequences can take up a significant amount of time, especially in the event of an unsuccessful erase or program step that must be repeated. This presents a problem when a microprocessor desires access to the flash memory array while the write state machine has control of the device.
This problem was alleviated by incorporating an erase suspend function within the write state machine. The microprocessor asserts an “erase suspend” command on the data bus, causing the write state machine to pause its erase sequence. The microprocessor may then read from a block in the flash memory array which is not being accessed by the write state machine. The interrupted erase sequence is then resumed once the microprocessor has finished with the read cycle.
Other advanced functions are carried out by the write state machine. In conventional flash memory devices these functions are laid out in an instruction circuit which contains the necessary logic to perform the instructions in the flash memory array. There exists a need for a more flexible and efficient system for storing these instructions.
SUMMARY OF THE INVENTION
The present invention relates to a system and method for a write state machine for flash memory. The system and method provide for a write state machine for efficiently carrying out the steps needed to program and erase a Flash memory. The instructions are stored in read only memory (ROM) contained within the write state machine. The write state machine further includes an address counter, to select the next instruction to be executed from the ROM, counters to cycle addresses in the flash memory array, and control logic to execute the current instruction.
With the use of the internal ROM, the write state machine can be manufactured ahead in the design cycle, regardless of the final form of the instructions for the flash memory. Further, the same write state machine can be re-used in different flash memory chips, requiring only the re-programming of the internal ROM with the necessary instructions.
REFERENCES:
patent: 4718037 (1988-01-01), Thaden
patent: 5355464 (1994-10-01), Fandrich et al.
patent: 5621687 (1997-04-01), Doller
patent: 5805501 (1998-09-01), Shiau et al.
patent: 5937424 (1999-08-01), Leak et al.
patent: 5940861 (1999-08-01), Brown et al.
patent: 6026016 (2000-02-01), Gafken
patent: 6081870 (2000-06-01), Roohparvar
patent: 6115292 (2000-09-01), Fukuda et al.
patent: 6201739 (2001-03-01), Brown et al.
patent: 6374337 (2002-04-01), Estakhri
Piersimoni Pietro
Pistilli Pasquale
Elms Richard
Morin & Oshinsky LLP
Nguyen Hien
Shapiro Dickstein
LandOfFree
Write state machine architecture for flash memory internal... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Write state machine architecture for flash memory internal..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Write state machine architecture for flash memory internal... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3072088