Write scheme for a double data rate SDRAM

Details Write scheme for a double data rate SDRAM Write scheme for a double data rate SDRAM

1998-12-03

2000-06-27

Phan, Trong

Static information storage and retrieval

Addressing

Sync/clocking

36523003, 36523008, 36518905, G11C 800

Patent

active

060814772

ABSTRACT:
A double data rate (DDR) synchronous dynamic random access memory (SDRAM) device with at least one memory bank is disclosed. Each memory bank is divided into two independent and simultaneously accessible memory planes. Input data aligned with the rising edge of a data strobe (DQS) and input data aligned with the falling edge of the DQS are separately latched coincident with the respective edges of the DQS. Using an internal clock, the latched input data is re-aligned and simultaneously sent to both planes of an addressed memory bank at the rising edge of the internal clock. With this configuration, the internal processing of the SDRAM is unaffected by latency variations of the DQS.

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