Write request interlock

Details Write request interlock Write request interlock

1994-09-09

1996-05-21

Heckler, Thomas M.

Boots, shoes, and leggings

364DIG2, 3649342, 36493471, 3649265, 3649393, G06F 700, G06F 112

Patent

active

055198546

ABSTRACT:
A CPU core 4 can operate at either an internal clock frequency fclk or an external clock frequency mclk. When operating at the internal clock frequency fclk, write request signals are buffered in a write buffer 10. When operating at the external clock frequency mclk, write request signals are unbuffered. In order to avoid write request signals reaching a signal bus 6 out of order, an interlock is provided between the two paths so that any pending write request signals in the write buffer 10 will serve to hold off any write request signals that may issue through the other path. When a write request signal generated at the external clock frequency is blocked, this serves to stall the CPU core 4 since the blocked external clock write request signal may give rise to an externally generated abort which would alter subsequent processing.

REFERENCES:
patent: 5124589 (1992-06-01), Shiomi et al.
patent: 5278789 (1994-01-01), Inoue et al.

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