Write ordering for microprocessor depending on cache hit and wri

Details Write ordering for microprocessor depending on cache hit and wri Write ordering for microprocessor depending on cache hit and wri

1991-10-11

1995-01-03

Harvey, Jack B.

Boots, shoes, and leggings

364239, G06F 1316

Patent

active

053793960

ABSTRACT:
An improvement in a microprocessor having a cache memory providing strong and weak write ordering modes. The microprocessor includes a terminal for receiving a signal indicating whether an external write buffer is empty and an internal signal indicating whether an internal write buffer is empty. Operation of the microprocessor is halted in the strong ordering mode if the write buffers are not empty and a hit condition occurs during a write cycle until the buffers are empty.

REFERENCES:
patent: 4805098 (1989-02-01), Mills, Jr. et al.
patent: 5125083 (1992-06-01), Fite et al.
patent: 5179679 (1993-01-01), Shoemaker
patent: 5222223 (1993-06-01), Webb, Jr. et al.
patent: 5224214 (1993-06-01), Rosich
patent: 5276849 (1994-01-01), Patel

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