Write latency tracking using a delay lock loop in a...

Details Write latency tracking using a delay lock loop in a... Write latency tracking using a delay lock loop in a...

2008-04-08

2008-04-08

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S193000

Reexamination Certificate

active

07355920

ABSTRACT:
A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the write path, and receives the system clock as its reference input. The DLL includes a modeled delay which models the delay in transmission of the internal Write Valid signal and system clock distribution to the deserializers in the data path portion of the write path, which is otherwise controlled by the intermittently asserted write strobe signal. With the input distribution delay of the system clock (Clk) and the write strobe (WS) matched by design, the distributed system clock and Write Valid signal are synchronized to the WS distribution path by means of the DLL delay with reference to the system clock input to the DLL. By backing the distribution delay out of system clock as sent to the deserializers, the write valid signal is effectively synchronized with the write strobe, with the effect that data will be passed out of the deserializer circuitry to the memory array on time and consistent with the programmed write latency.

REFERENCES:
patent: 6272070 (2001-08-01), Keeth et al.
patent: 6680866 (2004-01-01), Kajimoto
patent: 7113446 (2006-09-01), Fujisawa
patent: 2006/0013060 (2006-01-01), Li et al.

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